Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2001-04-02
2002-10-15
Le, N. (Department: 2858)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S014000, C438S018000
Reexamination Certificate
active
06465267
ABSTRACT:
FIELD OF THE INVENTION
The present specification relates generally to integrated circuits and methods of fabricating integrated circuits. More specifically, the present specification relates to a method of measuring gate capacitance in an integrated circuit to determine the electrical thickness of metal oxide semiconductor (MOS) gate dielectrics.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) include a multiple of transistors formed on a semiconductor substrate. Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally built on the top surface of a bulk substrate. The substrate is built to form impurity diffusion layers (i.e., source and drain regions). Between the source and drain regions is a conductive layer which operates as a gate for the transistor. The gate controls current in a channel between the source and drain regions.
Typically, an integrated circuit gate includes a gate electrode and a gate dielectric. The electrical thickness of MOS gate dielectrics can be an important parameter in the design and fabrication of the circuit. Such a thickness determination can be made from the gate capacitance in the inversion region. The inversion region refers to the characteristic of a transistor where the channel between active regions and under the gate is “inverted”. That is, the channel changes from a semiconductor P-type to N-type or N-type to P-type. Generally, the inversion region occurs when the gate to source voltage (V
gs
) is greater than or equal to the threshold voltage (V
th
).
However, as the physical thickness of gate dielectrics decreases (with the continuing decrease in integrated circuit size), gate leakage current due to direct tunneling increases. As a result, inversion region capacitance-voltage (C-V) characteristics can be so distorted (from gate leakage current) that the electrical thickness extraction or determination is less accurate.
Accordingly, there is a need for an improved technique for gate capacitance-voltage (C-V) measurement. Further, there is a need to use forwarded biased MOSFET structures to measure the inversion region gate capacitance at a reduced gate electrical field, thereby reducing the effects of gate leakage. Even further, there is a need for a method of measuring gate capacitance to more accurately determine the thickness of gate dielectrics.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of measuring gate capacitance to determine electrical thickness of a gate dielectric located in a gate structure of a metal oxide semiconductor field effect transistor (MOSFET). This method can include connecting a sensor to an integrated circuit gate structure and an active region located proximate the integrated circuit gate structure, applying forward body bias to the transistor to reduce the electrical field of the transistor at a gate inversion measuring point, and measuring capacitance with the sensor while the transistor receives the forward body bias.
Another exemplary embodiment relates to a method of measuring gate dielectric thickness in a metal oxide semiconductor field effect transistor (MOSFET). This method can include applying a voltage to a back gate of a transistor to reduce threshold voltage of the transistor, connecting a capacitance-voltage meter to the transistor, using the capacitance-voltage meter to measure the capacitance at a voltage above the threshold voltage of the transistor, and automatically determining thickness of a gate dielectric in the transistor using the measured capacitance.
Another exemplary embodiment relates to a method of automatically determining gate capacitance in a transistor having a gate structure including a gate dielectric. This method can include forward biasing a transistor having agate structure and a size greater than 100 square microns to reduce a voltage threshold of the transistor and measuring capacitance of the transistor at a voltage above the voltage threshold of the transistor.
Other features and advantages of the exemplary embodiments will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
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Wang Haihong
Xiang Qi
Advanced Micro Devices , Inc.
Hamdan Wasseem H.
Le N.
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