Method of measuring bias and edge overlay error for sub-0.5 micr

Details Method of measuring bias and edge overlay error for sub-0.5 micr Method of measuring bias and edge overlay error for sub-0.5 micr

1995-11-20

1998-05-26

Hantis, K.

Optics: measuring and testing

By alignment in lateral direction

With registration indicia

356374, 250548, 2505593, G01B 1100

Patent

active

057575070

ABSTRACT:
A method of determining bias or overlay error in a substrate formed by a lithographic process uses a pair of straight vernier arrays of parallel elements, a staggered vernier array of parallel elements, and optionally at least one image shortening array on the substrate. The ends of the elements form the array edges. The vernier arrays are overlaid such that: i) the elements of the straight and staggered arrays are substantially parallel; ii) one of the edges of the staggered array intersects with one of the edges of one the straight arrays; and iii) the other of the edges of the staggered array intersects with one of the edges of the other of the straight arrays. Bias or overlay error is determined by: i) locating the points of intersection of the edges of the second vernier array with the edges of the first vernier arrays and measuring the degree of separation of the intersection points, and ii) measuring the separation between adjacent edges of the image shortening array and the one of the first or second vernier arrays having corresponding element width and element spacing. Preferably, the location of the intersection points is measured relative to a fixed point on one of the arrays. Bias is proportional to the difference between the locations of the intersection points relative to a fixed point on one of the arrays. Overlay error is proportional to the sum of the locations of the intersection points relative to a fixed point on one of the arrays. A moire fringe pattern may be created by the degree of overlap of the straight and staggered arrays, and bias or overlay error may also be determined by measuring the fringe created in the moire fringe pattern.

REFERENCES:
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patent: 5262258 (1993-11-01), Yanagisawa
patent: 5402224 (1995-03-01), Hirukawa et al.
Ausschnitt, "Electrical Measurements for Characterizing Lithograph," VLSI Electronics, Microstructure Science, vol. 16, Chapter 8, pp. 320-356, 1987 .

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