Method of measuring an effective channel length and an...

Semiconductor device manufacturing: process – With measuring or testing

Reexamination Certificate

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C438S017000, C438S018000, C438S197000, C438S268000, C324S762010, C257SE21531

Reexamination Certificate

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07405090

ABSTRACT:
In a method of measuring an effective channel length and an overlap length, first to third metal-oxide semiconductor field effect transistors (MOSFETs) including first to third gate patterns, respectively, are formed on a substrate. A parasitic capacitance between the gate patterns and the substrate in the MOSFETs is determined based on first and second capacitances, which are measured by applying a first voltage between the gate patterns and the substrate. A second voltage is applied between the first gate pattern and the substrate in the first MOSFET and a third voltage between the third gate pattern and the substrate in the third MOSFET to measure capacitances. The capacitances are treated to obtain third and fourth capacitances excluding the parasitic capacitance. Overlap lengths of the gate patterns are obtained based on the third and fourth capacitances. Effective channel lengths of the gate patterns are obtained based on the overlap length.

REFERENCES:
patent: 6166558 (2000-12-01), Jiang et al.
patent: 6472233 (2002-10-01), Ahmed et al.
patent: 6514778 (2003-02-01), Huang et al.
patent: 2000-216258 (2000-08-01), None
patent: 2001-338986 (2001-12-01), None

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