Method of maufacturing a semiconductor device having a low resis

Details Method of maufacturing a semiconductor device having a low resis Method of maufacturing a semiconductor device having a low resis

1995-05-15

1996-08-13

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437241, 437913, 437983, H01L 218234

Patent

active

055455786

ABSTRACT:
A method for manufacturing a semiconductor device, e.g., an LDD transistor, which includes the steps of forming a gate insulating layer on a semiconductor substrate, forming a polysilicon layer on the gate insulating layer, forming a silicide layer on the polysilicon layer, etching the silicide layer to form a gate-patterned silicide layer, and over-etching the silicide layer to partially etch the polysilicon layer, to thereby form a step in the polysilicon layer, forming an oxidation-prevention spacer on sidewalls of the gate-patterned silicide layer and sidewalls of the polysilicon layer exposed by the step, etching the polysilicon layer, using the oxidation-prevention spacer as an etching mask, to thereby form a gate-patterned polysilicon layer, the gate-patterned silicide layer and the gate-patterned polysilicon layer together comprising a gate electrode, thermally oxidizing exposed portions of the gate insulating layer and exposed portions of the polysilicon layer, to thereby form an oxide layer, and, ion-implanting impurities into the semiconductor substrate, using the resultant structure as an ion-implantation mask, to thereby form source/drain regions in the semiconductor substrate, on opposite sides of the gate electrode.

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