Method of manufacturing wafer-level chip-size package and...

Details Method of manufacturing wafer-level chip-size package and... Method of manufacturing wafer-level chip-size package and...

2008-05-13

2008-05-13

Thai, Luan (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Encapsulating

C438S106000, C438S110000, C438S613000, C438S113000, C257S787000, C257S788000, C257SE21599, C257SE23124, C257S620000

Reexamination Certificate

active

10842523

ABSTRACT:
Provided are a method of manufacturing wafer-level chip-size packages and a molding apparatus suitable for practicing the method whereby a semiconductor wafer having a plurality of semiconductor chips formed thereon may be encapsulated. The semiconductor wafer, typically with a plurality of conductive bumps extending from the semiconductor chips, will be placed in a cavity formed between upper and lower molds. Injection molding of an encapsulant composition or compression molding of encapsulant sheets may then be used to apply encapsulating layers to the upper and lower surfaces of the semiconductor wafer in a substantially simultaneous manner, thereby reducing the likelihood of warping and mechanical damage to the semiconductor wafer. The wafer-level chip-size packages can then be separated from the encapsulated semiconductor wafer.

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Korean Office Action Jul. 7, 2005 for Korean Application No. 2003-0059832 (Complete English translation provided).

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