Method of manufacturing trench gate structure

Details Method of manufacturing trench gate structure Method of manufacturing trench gate structure

1999-12-15

2002-07-23

Goudreau, George (Department: 1763)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S751000, C438S723000, C438S724000, C438S719000, C438S692000, C438S753000, C438S756000, C438S757000, C438S734000

Reexamination Certificate

active

06423618

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention in general relates to a method of manufacturing a power metal-oxide-semiconductor field-effect transistor (MOSFET). In particular, the present invention relates to a method of manufacturing a trench power MOSFET and more particularly, to a method of manufacturing a trench gate structure of a trench power MOSFET.
2. Description of the Related Art
Currently, a power metal-oxide-semiconductor field-effect transistor (MOSFET) can be a high voltage device, and it can be operated at a voltage higher than 4500 volts. The conventional method for fabricating the power MOSFET is similar to the method for manufacturing a common semiconductor device. The gate structure of the power MOSFET is formed on the surface of the substrate, which is called a planar-gate structure. However, the method of fabricating the planar-gate structure may limit size reduction of the poly gate length and lead to a low cell packing density. Consequently, the fabrication of a trench power MOSFET, which can greatly reduce the size of the device, is the trend of the power device industry. The method of manufacturing a trench, double diffused MOS is disclosed in U.S. Pat. No. 5,567,634.
FIGS. 1A
through
1
E are schematic, cross-sectional views of the conventional process for manufacturing a trench gate structure of a trench power MOSFET.
As shown in
FIG. 1A
, a substrate
100
having an N-type epitaxial layer
101
thereon is provided. A silicon dioxide layer
102
is formed on the N-type epitaxial layer
101
. A silicon nitride layer
103
is formed on the silicon dioxide layer
102
. A silicon dioxide layer
104
is formed on the silicon nitride layer
103
.
As shown in
FIG. 1B
, a trench
105
is formed to penetrate through the silicon dioxide layer
104
, the silicon nitride layer
103
and the oxide layer
102
and into the epitaxial layer
101
. The oxide layer
104
is removed. A sacrificial oxide layer (not shown) is grown and then removed, which sacrificial oxide layer is used to restore the defects of the trench
105
. A gate oxide layer
106
is formed and is conformal to the trench
105
. A polysilicon layer
107
is formed over the substrate
100
and fills the trench
105
.
As shown in
FIG. 1C
, portions of the polysilicon layer
107
are removed to expose the surface of the silicon nitride layer
103
, and the surface of the remaining polysilicon layer
107
a
in the trench
105
is substantially level with the top surface of the silicon nitride layer
103
.
As shown in
FIG. 1D
, a portion of the polysilicon layer
107
a
is converted into a silicon dioxide layer
108
. The silicon nitride layer
103
is removed.
As shown in
FIG. 1E
, a P-type base region
109
is formed from the surface of the epitaxial layer
101
. An N
+
-type source region
110
is formed adjacent to the trench
105
in the P-type base region
109
. A spacer
111
is formed on the sidewall of the polysilicon layer
107
a
and the silicon dioxide layer
108
. A P
+
-type base ohmic contact
112
is formed on the side of the N
+
-type source region
110
. An aluminum film
113
is formed to cover the substrate
100
.
According to the above-mentioned method, the gate oxide layer on the bottom of the trench is thinner than the gate oxide layer on the sidewall of the trench, so the breakdown voltage of the gate oxide layer is decreased and the leakage current is increased. Furthermore, the accumulation of electrons at the bottom corner of the trench easily results in leakage current problems.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for manufacturing a trench power MOSFET. In one aspect of the present invention, the ability of the devices to resist the breakdown voltage is greatly enhanced and the problem of leakage can be overcome. Moreover, the capacitance between the gate structure and the drift region is decreased. Hence, the switching speed of the device is increased and the switching power loss is reduced.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, this invention provides a method for manufacturing a trench gate structure of a power metal-oxide-semiconductor field-effect transistor, which is formed on a substrate having a epitaxial layer thereon, a base region formed in the epitaxial layer, a source region formed in a portion of the base region, a first dielectric layer on the base region and the source region, and a second dielectric layer on. the first dielectric layer. Furthermore, a trench penetrates through the second and the first dielectric layers, the source region and the base region and into the epitaxial layer. A third dielectric layer is formed on the bottom of the trench. A conformal gate oxide layer is formed in the trench. A conformal polysilicon layer is formed on the second dielectric layer and in the trench. A fourth dielectric layer is formed on the polysilicon layer to fill the trench. Portions of the fourth dielectric layer and the polysilicon layer are removed until the surfaces of the fourth dielectric layer and the polysilicon layer are substantially level with the surface of the base region.
A method for manufacturing a trench gate structure of a power metal-oxide-semiconductor field-effect transistor is suitable for formation on a substrate having a epitaxial layer thereon, a base region formed in the epitaxial layer, a source region formed in a portion of the base region, a first dielectric layer on the base region and the source region, a second dielectric layer on the first dielectric layer and a trench penetrating through the second and the first dielectric layers, the source region and the base region and into the epitaxial layer. A third dielectric layer is formed on the bottom of the trench. The second dielectric layer is removed. A conformal gate oxide layer is formed in the trench. A conformal polysilicon layer is formed on the first dielectric layer and in the trench. A fourth dielectric layer is formed on the polysilicon layer to fill the trench. The fourth dielectric layer and the polysilicon layer are patterned so that the remaining fourth dielectric layer and polysilicon layer extending on the first dielectric layer are wider than the trench.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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