Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-04-20
2002-12-31
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S030000
Reexamination Certificate
active
06500701
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-129661, filed Apr. 28, 2000; and No. 2000-165516, filed Jun. 2, 2000, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor panel used in, for example, an active matrix type liquid crystal display device, particularly, to a method of manufacturing a thin film transistor panel, which permits lowering the manufacturing cost of a thin film transistor having a protective film of the channel region.
2. Description of the Related Art
In manufacturing a thin film transistor panel applied to an active matrix type liquid crystal display device, a transparent substrate is prepared consisting of, for example, glass and providing the base of the thin film transistor panel. In order to improve productivity, a large transparent substrate having a size corresponding to a plurality of thin film transistor panels is prepared, and the portions corresponding to a plurality of panels are collectively prepared up to a predetermined manufacturing step, followed by dividing the large transparent substrate into individual panels for application of the subsequent manufacturing steps. Also, in the case of manufacturing a thin film transistor panel equipped with a thin film transistor acting as a switching element, an anodic oxide film is formed on the surface of, for example, a gate line (scanning signal line) including the gate electrode of the thin film transistor so as to improve the breakdown voltage. Further, insulation breakdown takes place in the thin film transistor or the voltage-current characteristics of the thin film transistor are changed by static electricity generated when, for example, the oriented film is subjected to a rubbing treatment before the large transparent substrate is divided into the individual panels, or by the divided individual panels contacting another substance charged with a high voltage of, for example, static electricity. Under the circumstances, measures against static electricity are taken.
FIG. 20
, which illustrates the prior art, is a plan view showing the equivalent circuit of a thin film transistor panel under the state that pixel electrodes, etc. are formed on a glass substrate having a size corresponding to a plurality of thin film transistor panels. A glass substrate
1
having a size corresponding to a plurality of thin film transistor panels is finally cut along a cut line
2
denoted by a dot-and-dash line so as to be divided into individual panels. In this case, the region surrounded by the cut line
2
forms a panel forming region
3
and the region surrounding the panel forming region
3
forms a panel non-forming region
4
. Also, that region of the panel forming region
3
which is surrounded by a two dots-and-dash line forms a display region
5
, and the region surrounding the display region
5
forms a non-display region
6
.
Arranged within the display region
5
are a plurality of pixel electrodes
7
arranged to form a matrix, a plurality of thin film transistors
8
connected to these pixel electrodes
7
, a plurality of scanning signal lines
9
arranged in the row direction for supplying a scanning signal to the thin film transistors
8
, a plurality of data signal lines
10
arranged in the column direction for supplying a data signal to the thin film transistors
8
, a plurality of auxiliary capacitance lines
11
arranged in the row direction and forming an auxiliary capacitance section Cs between the pixel electrode
7
and the auxiliary capacitance line
11
, a protective ring
13
including a jumper line
12
arranged to surround a plurality of the pixel electrodes
7
, a plurality of protective elements
14
arranged on the outside of the protective ring
13
and each consisting of two protective thin film transistors arranged to face each other with the scanning signal line
9
interposed therebetween, and a plurality of protective elements
15
arranged on the outside of the protective ring
13
and each consisting of two protective thin film transistors arranged to face each other with the data signal line
10
interposed therebetween. Further, power supply lines
16
are arranged to form a lattice within the panel non-forming region
4
.
The left edge portion of each of the scanning signal lines is connected to the power supply line
16
via a connection pad (scanning electrode terminal)
18
on the output side arranged within a semiconductor chip mounting region
17
denoted by a dotted line within the non-display region
6
. The upper edge portion of each of the data signal lines
10
is connected to the power supply line
16
via a connection pad (data electrode terminal)
20
on the output side arranged within a semiconductor chip mounting region
19
denoted by a dotted line within the non-display region
6
. Connection pads
21
,
22
on the input side, which are arranged within the semiconductor chip mounting regions
17
,
19
, respectively, are connected to external connection terminals
23
formed at predetermined positions within the non-display region
6
via wirings
24
. These external connection terminals
23
are connected to the power supply line
16
. The left edge portion of each of the auxiliary capacitance lines
11
is connected to the power supply line
16
via a common line
25
and a connection pad
26
, which are arranged on the outside of the right side portion of the protective ring
13
. Incidentally, the common line
25
is connected to the protective ring
13
in some cases.
The gate electrode G and the source electrode S of the protective thin film transistor on the upper side, which is included in the protective element
14
arranged on the side of the scanning signal line, are connected to the scanning signal line
9
, and the drain electrode of the particular protective thin film transistor is connected to the protective line
13
. On the other hand, the gate electrode G and the source electrode S of the lower protective thin film transistor, which is included in the protective element
14
on the side of the scanning signal line, are connected to the protective ring
13
, and the drain electrode D of the particular thin film transistor is connected to the scanning signal line
9
. Further, the gate electrode G and the source electrode S of the protective thin film transistor on the left side, which is included in the protective circuit
15
on the side of the data signal line, are connected to the protective ring
13
, and the drain electrode D of the particular thin film transistor is connected to the data signal line
10
. Still further, the gate electrode G and the source electrode S of the protective thin film transistor on the right side, which is included in the protective element
15
arranged on the side of the data signal line, are connected to the data signal line
10
, and the drain electrode D of the particular thin film transistor is connected to the protective ring
13
.
The method of manufacture of a thin film transistor panel of the construction described above will now be described with reference to FIG.
21
. In the first layer forming step S
1
shown in
FIG. 21
, an Al-based metal film (not shown) such as an Al film or an Al alloy film is formed on the upper surface of a glass substrate. Then, in the first photoresist forming step S
2
shown in
FIG. 21
, a first photoresist film is formed on the upper surface of the Al-based metal film. Further, in the scanning signal line forming step S
3
shown in
FIG. 21
, the Al-based metal film is etched with the first photoresist film used as a mask, followed by peeling off the first resist film.
As a result, formed on the upper surface of the glass substrate
1
are the gate electrode G of the thin film transistor, the scanning signal line
9
, the auxiliary capacitance line
11
, a lower protective ring
13
a
, and a low
Higashi Toshiaki
Miyakawa Tatsuya
Casio Computer Co. Ltd.
Frishauf Holtz Goodman & Chick P.C.
Tsai Jey
LandOfFree
Method of manufacturing thin film transistor panel having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing thin film transistor panel having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing thin film transistor panel having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2919665