Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2005-12-20
2005-12-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C257S072000
Reexamination Certificate
active
06977192
ABSTRACT:
In manufacturing a thin film semiconductor device, a gate electrode forming step, a gate insulating film forming step, an amorphous semiconductor film forming step, a crystalline semiconductor film forming step, and an insulating film forming step are performed continuously without breaking vacuum.
REFERENCES:
patent: 4862237 (1989-08-01), Morozumi
patent: 5036370 (1991-07-01), Miyago et al.
patent: 5124823 (1992-06-01), Kawasaki et al.
patent: 5198694 (1993-03-01), Kwasnick et al.
patent: 5362660 (1994-11-01), Kwasnick et al.
patent: 5471330 (1995-11-01), Sarma
patent: 5473168 (1995-12-01), Kawai et al.
patent: 5536932 (1996-07-01), Hack et al.
patent: 5567633 (1996-10-01), Gosain et al.
patent: 5576222 (1996-11-01), Arai et al.
patent: 5656824 (1997-08-01), Den Boer et al.
patent: 5686335 (1997-11-01), Wuu et al.
patent: 5805252 (1998-09-01), Shimada et al.
patent: 6146929 (2000-11-01), Oana et al.
patent: 6204519 (2001-03-01), Yamazaki et al.
patent: 6337229 (2002-01-01), Yamazaki et al.
patent: 6392810 (2002-05-01), Tanaka
patent: 6458635 (2002-10-01), Yamazaki et al.
patent: 6524877 (2003-02-01), Nakazawa et al.
patent: 6528357 (2003-03-01), Dojo et al.
patent: 2001/0038099 (2001-11-01), Yamazaki et al.
patent: 2003/0040150 (2003-02-01), Yamazaki et al.
patent: 3-220529 (1991-09-01), None
patent: 04-505832 (1992-10-01), None
patent: 04-326769 (1992-11-01), None
patent: 542271 (1993-05-01), None
patent: 5-235355 (1993-09-01), None
patent: 6-77483 (1994-03-01), None
patent: 6-77485 (1994-03-01), None
patent: 07-038110 (1995-02-01), None
patent: 09-246564 (1997-09-01), None
patent: WO 92/06505 (1992-04-01), None
Aoyama et al., “Inverse Staggered Polycrystalline and Amorphous Silicon Double Structure Thin Film Transistors,” Applied Physics Letters, vol. 66, No. 22, pp. 3007-3009.
Hayashi H. et al., Fabrication of Low-Temperature Bottom-Gate Poly-Si TFTs on Large-Area Substrate by Linear-Beam Excimer Laser Crystallization and Ion Doping Method, Dec. 1995, Washington, D.C.
Japan 04-326769: English abstract, DIALOG(R) File 352: Derwent WPI, Accession No. 009302268 (2004).
Japan 04-505832: English abstract, DIALOG(R) File 352: Derwent WPI, Accession No. 009023746 (2004) and family to US 5,198,694 (Desig. ID “AC”), US 5,362,660 (Desig. ID “AD”) and WO 92/06505 (Desig. ID “AP”).
Japan 07-038110: English abstract, DIALOG(R) File 352: Derwent WPI, Accession No. 010211012 (2004).
Japan 09-246564: English abstract, DIALOG(R) File 352: Derwent WPI; Accession No. 011542820 (2004) and family to US 6,204,519 (Desig. ID “AE”), US 6,458,635 (Desig. ID “AF”), US 2001/0038099 (Desig. ID “AB”) and US 2003/0040150 (Desig. ID “AA”).
Fukada Takeshi
Hamatani Toshiji
Yamazaki Shunpei
Fish & Richardson P.C.
Le Thao P.
Nelms David
Semiconductor Energy Laboratory Co,. Ltd.
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