Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-07-05
2001-02-27
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S594000, C438S266000
Reexamination Certificate
active
06194300
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing flash memory. More particularly, the present invention relates to a method of manufacturing the floating gate of a split-gate flash memory.
2. Description of Related Art
Nonvolatile memory is widely used in all kinds of electronic devices for storing structural data, program data and other repeatedly used data. Nonvolatile memory includes erasable programmable read-only memory (EPROM) and electrically erasable programmable ROM (EPROM), both having a flash memory structure.
In general, a flash memory unit has a floating gate and a control gate. The floating gate is made from polysilicon and is designed to hold electric charges. The control gate, on the other hand, is designed to control the storage and retrieval of data. The floating gate is under the control gate and is generally in a floating state not connected to any external circuit. The control gate is normally connected to a word line. Since data can be stored into, read from or removed from a flash memory a multiple of times, production growth is fast in the semiconductor industry.
FIG. 1
is a schematic cross-sectional view of a conventional flash memory unit. As shown in
FIG. 1
, a tunnel oxide layer
105
, a floating gate
110
, a polysilicon oxide layer
120
, an oxide
itride/oxide dielectric layer
125
and a control gate
130
are formed over a substrate
100
. The substrate
100
also has a source terminal
135
and a drain terminal
140
.
To erase data within the flash memory unit, the control gate
130
is connected to an external voltage source of about
14
V. Utilizing the pointed tip
118
on the floating gate
110
to produce an intense electric field, electrons within the floating gate
110
are accelerated and injected into the control gate
130
. Hence, the pointed tip structure
115
on the floating gate
110
is important for determining the efficiency of data removal.
FIGS. 2A through 2C
are schematic cross-sectional views showing the progression of steps for producing a conventional split-gate flash memory.
As shown in
FIG. 2A
, a tunnel oxide layer
220
, a doped polysilicon layer
225
and a silicon nitride layer
230
are formed in sequence over a substrate
200
. Microlithographic and etching processes are carried out next to pattern the silicon nitride layer
230
, thereby forming an opening
235
.
A thermal oxidation is carried out, as shown in FIG.
2
B. Hence, the doped polysilicon layer
225
that is exposed by the opening
235
is oxidized to form a polysilicon oxide layer
240
.
The silicon nitride layer
230
is selectively removed using hot phosphoric acid. Using the polysilicon oxide layer
240
as an etching mask, the doped polysilicon layer
225
is etched to form a floating gate
225
a
, as shown in FIG.
2
C.
Since the polysilicon oxide layer
240
is conventionally formed by a thermal oxidation, the uniformity of the layer, which is affected by doping concentration and size of the grains inside the layer, is difficult to control. Hence, the flash memory formed by the conventional method has an unstable and reliability issue.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of producing the floating gate of a split-gate flash memory that has higher production yield and improved reliability.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of producing the floating gate of a split-gate flash memory. A patterned sacrificial layer is formed over a substrate so that a portion of the substrate is exposed. A doped polysilicon layer is formed above the substrate. The doped polysilicon layer above the sacrificial layer is removed by chemical-mechanical polishing, for example. An insulation layer is formed over the substrate. The insulation layer above the sacrificial layer is again removed by chemical-mechanical polishing, for example. The exposed doped polysilicon layer is removed to form the floating gate. Lastly, the sacrificial layer is removed.
This invention also provides an alternative method of producing the floating gate of a split-gate flash memory. A sacrificial layer is formed over a substrate. The sacrificial layer is patterned to form a plurality of openings that expose a portion of the substrate. A doped polysilicon layer and an insulation layer are formed in sequence over the substrate. The doped polysilicon layer and the insulation layer above the sacrificial layer are removed by chemical-mechanical polishing, for example. A portion of the doped polysilicon layer is removed to form a floating gate using the insulation layer as a mask. Lastly, the sacrificial layer is removed.
This invention does away with the thermal oxidation step in the conventional method used to form polysilicon oxide. Instead, a patterned sacrificial layer is formed over the substrate, and then a doped polysilicon layer and insulation layer are formed in sequence over the sacrificial layer. The insulation layer and the doped polysilicon layer above the sacrificial layer are removed by separate or a single chemical-mechanical polishing so that sharp corner can still be maintained and be easily controlled compared with the conventional polyoxidation layer near the upper peripheral region of the floating gate, which facilitates the erasure of stored data from the flash memory.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4997781 (1991-03-01), Tigelaar
patent: 5143860 (1992-09-01), Mitchell et al.
patent: 5476801 (1995-12-01), Keshtbod
patent: 5496753 (1996-03-01), Sakurai et al.
patent: 5707897 (1998-01-01), Lee et al.
patent: 5767005 (1998-06-01), Doan et al.
patent: 5907775 (1999-05-01), Tseng
patent: 5915177 (1999-06-01), Tseng
patent: 6008112 (1999-12-01), Acocella et al.
patent: 6069040 (2000-05-01), Miles et al.
patent: 6090668 (2000-07-01), Lin et al.
Hung Chih-Wei
Shih Chi-Jen
Booth Richard
Huang Jiawei
Patents J C
Taiwan Semiconductor Mfg. Co. Ltd.
LandOfFree
Method of manufacturing the floating gate of split-gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing the floating gate of split-gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing the floating gate of split-gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2593221