Method of manufacturing submicron channel transistors

Details Method of manufacturing submicron channel transistors Method of manufacturing submicron channel transistors

1979-11-14

1982-02-02

Massie, Jerome W.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29571, 156653, 156657, 1566611, 156662, 357 54, 357 59, 427 94, 427399, H01L 21308

Patent

active

043137822

ABSTRACT:
A method for fabricating a submicron short channel MOS device is described wherein a plural or multilevel insulator layer, having a thickness of about 100-200 angstroms, is interposed between the polycrystalline silicon gate member and the substrate to function as a gate insulator and in addition, serving to protect the body of the semiconductor from becoming inadvertently doped during the processing steps.

REFERENCES:
patent: 3738880 (1973-06-01), Laker
patent: 3783047 (1974-01-01), Paffen et al.
patent: 3903325 (1975-09-01), Horiuchi
patent: 3967981 (1976-07-01), Yamazaki
patent: 4051273 (1977-09-01), Abbas et al.
patent: 4124833 (1978-11-01), Nicholas
patent: 4151537 (1979-04-01), Goldman et al.
patent: 4162504 (1978-07-01), Hsu
patent: 4201603 (1980-05-01), Scott et al.
Baker et al., "Field Effect Transistor", IBM Technical Disclosure Bulletin, vol. 11, No. 7 (12/68), p. 849.

Affiliated with

Also associated with

Rating

Method of manufacturing submicron channel transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing submicron channel transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing submicron channel transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1820149