Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-06-19
2004-08-24
Vu, Hung (Department: 2811)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S648000, C438S685000
Reexamination Certificate
active
06780769
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for connecting interconnect lines and more particularly, to a technique for connecting a pair of interconnect lines in a semiconductor device stacked in a direction of a thickness of the semiconductor device, for example.
2. Description of the Background Art
In a semiconductor integrated circuit undergoing development in scaledown, attention has been directed to interconnection delay as a factor in inhibiting increase in operating speed of a device. The delay in semiconductor integrated circuit is the sum of the delay in transistor as a semiconductor element and the delay in interconnection for connecting transistors. When it is required to reduce dimensions of each type of element for constituting the semiconductor device for realizing scaledown, the delay in transistor is reduced according to a scaling law. In contrast, the interconnection delay determined in proportion to the product of interconnection resistance and interconnection capacitance is increased. In view of this, it follows that the reduction in interconnection resistance brings reduction in interconnection delay, offering enhanced speed of the semiconductor device.
Instead of aluminum-based material conventionally employed, it has been suggested to employ copper (Cu) as a material for interconnection having a lower resistivity. An interconnect line made of copper (hereinafter referred to as “copper interconnect line”) is desirable as compared with an interconnect line made of aluminum-based material in that it has a high resistance to electromigration.
As compared with aluminum-based interconnection material, however, it is hard to perform dry etching on copper. For this reason, in order to form the copper interconnect line, a so-called “Damascene” technique is employed in many cases. According to this technique, a trench is provided in an insulating film. This trench is filled with metal and a redundant part of metal is removed by polishing, for example. Then the metal remains in the trench is employed as an interconnect line.
Copper is further characterized in that when it goes into silicon, a deep level is formed in a band gap of silicon. Therefore, copper included in a MOS transistor for constituting an integrated circuit will cause a serious deterioration in characteristics of the MOS transistor. In addition, copper is likely to diffuse into a silicon oxide film generally used as an insulating layer of the semiconductor device. In view of the foregoing, it is necessary to surround the copper interconnect line with a film for preventing diffusion of copper.
FIG. 13
is a sectional view illustrating the structure of a pair of copper interconnect lines provided by Damascene technique. An insulating film
101
, a first insulating barrier layer
104
, an interlayer insulating film
105
and a second insulating barrier layer
108
are stacked in this order. Also provided under the insulating film
101
(that is, on the side opposite to the second insulating barrier layer
108
) is a semiconductor substrate (not shown) for holding a semiconductor element formed therein.
A copper interconnect line
102
is embedded in the insulating film
101
and the bottom surface and side surfaces of the first copper interconnect line
102
are covered with a first conductive barrier layer
103
. A second copper interconnect line
106
is embedded in the interlayer insulating film
105
and the bottom surfaces and side surfaces of the second copper interconnect line
106
are covered with a second conductive barrier layer
107
. The first copper interconnect line
102
and the second copper interconnect line
106
are positioned adjacent to each other through the second conductive barrier layer
107
and electrically connected to each other. Except this neighboring area, the first copper interconnect line
102
and the second copper interconnect line
106
are isolated from each other by the first insulating barrier layer
104
and the interlayer insulating film
105
. When further copper interconnect line is provided in the interlayer insulating film
105
other than the second copper interconnect line
106
, it is a matter of course that the copper interconnect other than the second copper interconnect line
106
and the second copper interconnect line
106
are to be isolated from each other by the interlayer insulating film
105
.
A silicon oxide film is applicable as the insulating film
101
and the interlayer insulating film
105
, for example. As the first insulating barrier layer
104
and the second insulating barrier layer
108
, a silicon nitride film and a silicon carbide film are applicable, for example, for increasing strength of the insulating film
101
and the interlayer insulating film
105
and for obtaining isolation between the layers. As the first conductive barrier layer
103
and the second conductive barrier layer
107
, a metallic compound having conductivity is employed in many cases for reducing interconnection resistance and establishing electrical connection between the first copper interconnect line
102
and the second copper interconnect line
106
while preventing diffusion of copper from the copper interconnect lines into the insulating film
101
and the interlayer insulating film
105
.
However, the silicon oxide film to be employed as the insulating film
101
and the interlayer insulating film
105
has a thermal expansion coefficient of 1.21×10
−7
/K while copper has a thermal expansion coefficient of 1.67×10
−5
/K. That is, the thermal expansion coefficient of copper is considerably higher than that of the silicon oxide film. After formation of the copper interconnect lines, thermal processings are performed for forming the insulating films or in an atmosphere including hydrogen and in a temperature of about 400° C., for example, for recovering damage to the semiconductor element not shown such as a transistor that is caused during formation of the copper interconnect lines. Further, the rise in temperature is caused by Joule heat that is generated upon energizing the semiconductor integrated circuit. It view of these, it follows that there occurs tensile stress in the copper interconnect lines.
Turning to the metallic compound to be employed as the first conductive barrier layer
103
and the second conductive barrier layer
107
having the property of preventing diffusion of copper into the outside, it generally has poor adhesion to copper. Further, the second copper interconnect line
106
has a small diameter at the region neighboring on the first copper interconnect line
102
and the tensile stress described above is likely to be concentrated especially at this region. As a result, a void may be generated in the second copper interconnect line
106
at the region of a small diameter thereof (contact hole). This void will cause failure in electrical connection between the second copper interconnect line
106
and the first copper interconnect line
102
.
As a countermeasure against the foregoing, a technique of using a stacked layer including titanium having good adhesion to copper and a metallic compound sandwiched between titanium has been suggested as a structure especially of the second conductive barrier layer
107
. According to the structure illustrated in
FIG. 13
, Japanese Patent Application Laid-Open No. 2000-183064 discloses, for example, the technique of providing a barrier layer having a three sublayer structure of Ti/TiN/Ti between the second copper interconnect line
106
and the first copper interconnect line
102
.
In the structure having direct connection between titanium (Ti) and copper, however, there arises a problem in that titanium easily diffuses into the copper interconnect lines to thereby form an alloy. The alloy formed in this way has a resistivity higher than that of copper and therefore, causes rise in interconnection resistance and in interface resistance at the contact hole.
SUMMARY OF THE INVENTION
A first aspect of the presen
Fujisawa Masahiko
Morimoto Noboru
Ohsaki Akihiko
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
Vu Hung
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