Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2001-04-18
2003-04-22
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S060000, C438S075000, C438S144000, C438S307000, C438S525000, C438S529000
Reexamination Certificate
active
06551910
ABSTRACT:
RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P2000-117326 filed Apr. 19, 2000, which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a solid-state image pickup device, and particularly to a method of manufacturing a sensor portion in a solid-state image pickup device having a virtual gate structure that a substrate surface side of a sensor area is pinned.
In a solid-state image pickup device, for example, a CCD (Charge Coupled Device) type image pickup device, a sensor photodetecting portion for performing photoelectric conversion (hereinafter referred to as “sensor portion”) comprises an n-type layer for photoelectrically converting incident light to charges and accumulating the charges thus obtained, a p-type layer for forming an overflow barrier, and a p-type high-concentration (p+) layer for pinning the surface of an Si substrate so as to suppress emission of charges (dark current) occurring due to interface level. Here, if the pinning effect of the p+ layer on the surface of the Si substrate is insufficient, the dark current component would be increased and the image quality under a dark condition is adversely effected.
In a case where a profile of a sensor portion is formed, it is general that a transfer electrode of a vertical transfer portion is formed of, for example, polysilicon, and then ion implantation of impurities is carried out in self-alignment with the transfer electrode as a mask, excluding an overflow barrier. Further, the ion implantation to form the profile aims to prevent channeling to Si crystal. In order to offset a p+ region and an n+ region with each other intentionally, the ion implantation is generally carried out at an inclined (tilt) angle of several degrees with respect to the surface of the Si substrate from a predetermined direction.
This offset can reduce a read-out voltage when charges accumulated in the sensor portion are read out to a vertical transfer channel, and also adjust suppression of the blooming phenomenon that charges overflow into the vertical transfer channel at the time when a large amount of light is incident. However, the optimum offset combination (p+, n+ implantation directions) is three-dimensionally determined by a unit cell size and the potential of the sensor portion and the vertical transfer channel, and thus the optimum combination of the ion implantation directions would be varied in accordance with a profile design.
Besides, the shape of the transfer electrode of the vertical transfer portion simultaneously determines the shape of the sensor area. At this time, for an ideal shape, it is actual that constriction occurs in the opening shape of the sensor portion due to working problems such as a photolithography resolution problem, a matching precision problem, etc. as shown in FIG.
7
. Accordingly, if impurities are doped from one direction by ion implantation, the impurities would not be doped into the constriction site, and thus an impurities-unformed area occurs.
Further, since the transfer electrode of the vertical transfer portion has a thickness of about 300 nm to 700nm, shadow occurs due to the film thickness by the effect of the tilt angle when the ion implantation is carried out. Therefore, an area into which no impurities are implanted necessarily occurs at the edge portion of the vertical transfer electrode although the area is small as shown in FIG.
8
. Particularly, in cooperation with the lower implantation energy of the ion doping of boron used to form the p+ layer on the surface of the substrate, a p+ unformed area is liable to occur at the edge of the vertical transfer electrode.
It is somewhat expected that impurities are diffused in the lateral direction due to a thermal treatment after the ion implantation. However, since the impurities-unformed area exists at the edge of the transfer electrode of the vertical transfer portion, it is liable to be depleted when a positive voltage is applied to the transfer electrode concerned. Therefore, the pinning effect would be insufficient if no countermeasure is taken. As a result, dark current is liable to occur, and also the dark current characteristic becomes unstable due to dispersion of the work shape of the vertical transfer electrode, so that the image quality is adversely effected.
SUMMARY OF THE INVENTION
The present invention has been implemented in view of the above circumstances, and has an object to provide a method of manufacturing a solid-state image pickup device which can stably suppress dark current occurring in a sensor portion.
In order to achieve the above object, a method of manufacturing a solid-state image pickup device having a virtual gate structure that a substrate surface side of a sensor area is pinned, is characterized in that when ion implantation of impurities to form a profile for pinning the substrate surface side of the sensor area is carried out at a predetermined implantation angle with respect to the surface of the substrate, the ion implantation is carried out while its operation is divided to plural times (stages) and also carried out from multiple ion implantation directions.
In the solid-state image pickup device having the virtual gate structure, when impurities to form the profile for pinning the substrate surface side of the sensor area are doped by ion implantation in the process of forming the sensor portion, channeling can be prevented by inclining the ion implantation direction with respect to the surface of the substrate by several angles. The ion implantation is carried out while being divided into plural times (plural sub ion implantation operations) and also the respective sub ion implantation operations are carried out from different directions (i.e., the ion implantation is divisively carried out from multiple ion implantation directions), whereby no impurities-unformed area occurs in any area of the sensor area.
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patent: 5705410 (1998-01-01), Guegan
patent: 6114210 (2000-09-01), Wu et al.
patent: 6333526 (2001-12-01), Tanabe
patent: 6194278 (2002-02-01), Rengarajan
patent: 6221686 (2002-04-01), Drowley et al.
Depke Robert J.
Holland & Knight LLC
Niebling John F.
Simkovic Viktor
Sony Corporation
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