Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1998-03-05
2002-04-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
Reexamination Certificate
active
06365488
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a silicon-on-insulator (SOI) device having a buried layer in the fabrication of integrated circuits.
(2) Description of the Prior Art
As 3C (computer, communication, and consumer) integration becomes a worldwide trend, Bipolar Junction Transistor (BJT) devices are coming into high demand. Because of their good device isolation properties and resulting superb device performance characteristics, silicon-on-insulator (SOI) wafers are becoming more and more popular. Silicon-on-insulator technology is discussed in
Silicon Processing for the VLSI Era—Volume II,
_by Stanley Wolf, Lattice Press, Sunset Beach, Calif., c. 1990, on pages 66-78. Two of the many methods of making SOI wafers will be described with reference to
FIGS. 1A
,
1
B,
2
A,
2
B, and
2
C.
Referring now more particularly to
FIG. 1A
, there is shown a semiconductor substrate
1
, preferably composed of monocrystalline silicon. A layer of silicon oxide
2
is formed on the surface of the substrate. A second monocrystalline substrate
3
has a silicon oxide layer
4
formed thereon. The first substrate
1
is turned upside down and the two substrates are joined together at the surface of their oxide layers by pressurizing and strengthening during later annealing. The substrate
1
is etched back or polished to reduce its thickness, as shown in FIG.
1
B. This method can be referred to as the bonded and etched back SOI (BESOI).
A second method is known as the Unibond™ method. The SMART-CUT Unibond™ method is discussed in the three papers, “Silicon on Insulator Material Technology,” by M. Bruel,
Electronics Letters, Vol
. 31, No. 14, Jul. 6, 1995, pp. 1201-1202, ““SMART CUT’: A Promising New SOI Material Technology,” by M. Bruel et al,
Proceedings
1995
IEEE International SOI Conference
, October 1995, pp. 178-179, and “Cleaning and Polishing as Key Steps for SMART-CUT SOI Process,” by H. Moriceau et al,
Proceedings
1996
IEEE International SOI Conference
, October 1996, pp. 152-153. Referring now to
FIG. 2A
, there is shown a monocrystalline silicon semiconductor substrate
1
. An oxide layer
2
is grown on the surface of the substrate
1
. Hydrogen ions are implanted into the wafer to a level
5
where splitting is designed to take place. Referring to
FIG. 2B
, a second monocrystalline substrate
3
has a silicon oxide layer
4
formed thereon. The first substrate
1
is turned upside down and the two substrates are joined together at the surface of their oxide layers by pressurizing and strengthening during later annealing. During a heat treatment at 400-600° C., the wafer
1
will split at the level of the hydrogen ion penetration
5
, leaving behind a thin layer of silicon
6
, as shown in FIG.
2
C. The substrate
1
that has been split off is re-usable.
In order to make BJT and BICMOS integrated circuit devices of high performance using SOI wafers, it is necessary to make SOI wafers having a buried layer structure within. U.S. Pat. No. 5,488,012 to McCarthy teaches a method of growing a sequence of single or multiple etch stop layers ending with a thin silicon layer on a silicon substrate. The silicon layer is bonded to a glass substrate and the silicon substrate is removed. U.S. Pat. No. 5,286,670 to Kang et al shows a method of forming a semiconductor device having electrical elements buried within a SOI substrate. A layer of polysilicon covers the buried electrical elements and is polished before being bonded to a semiconductor substrate. U.S. Pat. No. 5,360,752 to Brady et al teaches a method of radiation hardening the buried oxide in a SOI structure by implanting ions into the oxide layer.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming a silicon-on-insulator device having a buried layer in the fabrication of an integrated circuit.
Another object of the present invention is to provide a method of forming a silicon-on-insulator device having a buried layer formed by ion implantation in the fabrication of an integrated circuit.
Yet another object of the present invention is to provide a method of forming a silicon-on-insulator device having a buried layer formed by silicide in the fabrication of an integrated circuit.
A further object of the invention is to provide a method of forming a bonded and etched back silicon-on-insulator device (BESOI) having a buried layer in the fabrication of an integrated circuit.
A still further object of the invention is to provide a method of forming a Unibond™ silicon-on-insulator device having a buried layer in the fabrication of an integrated circuit.
In accordance with the objects of this invention the method of forming a silicon-on-insulator device having a buried layer is achieved. Ions are implanted into a first semiconductor substrate where it is not covered by a photoresist mask to form implanted regions. Alternatively, a silicide layer over the first semiconductor substrate is patterned to leave silicide regions. A first oxide layer is formed overlying the first semiconductor substrate whereby the implanted regions or the silicide regions form the buried layer structure. A second oxide layer is formed overlying a second semiconductor substrate. The first and second oxide layers are bonded together to form the wafer, using either the bond and etch back or the Unibond™ method to complete formation of an silicon-on-insulator wafer having a buried layer structure in the fabrication of an integrated circuit.
REFERENCES:
patent: 4772571 (1988-09-01), Scovell et al.
patent: 5374564 (1994-12-01), Bruel
patent: 5591678 (1997-01-01), Bendik et al.
patent: 5618739 (1997-04-01), Takahashi et al.
patent: 5807783 (1998-09-01), Gaul et al.
patent: 5851894 (1998-12-01), Ramm
patent: 5863832 (1999-01-01), Doyle et al.
patent: 5904495 (1999-05-01), Burke et al.
patent: 6030865 (2000-02-01), Hashimoto et al.
S. Wolf “Silicon Processing For The VLSI Era” vol. 2, Lattice Press, Sunset Beach, CA, 1990, pp. 66-78.
M. Bruel, “Silicon on Insulator Material Technology”, Electronics Letters, vol. 31, No. 14, Jul. 6 1995, pp. 1201-1202.
M. Bruel, “SMARTCUT: A Promising New SOI Material Technology” Proceedings 1995 IEEE International SOI Conf. Oct. 1995, pp. 178-179.
H. Moriceau et al., “Cleaning and Polishing as Key Steps for SMART-CUT SOI Process”, Proceedings 1996 IEEE International SOI Conference, Oct. 1996, pp. 152-153.
Ackerman Stephen B.
Fourson George
Industrial Technology Research Institute
Pike Rosemary L. S.
Saile George O.
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