Method of manufacturing silicon carbide self-aligned...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S044000, C438S222000, C438S666000, C438S903000, C438S969000, C257S592000, C257S665000, C257S734000, C257SE21135, C257SE23141

Reexamination Certificate

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07994017

ABSTRACT:
A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.

REFERENCES:
patent: 6096607 (2000-08-01), Ueno
patent: 6127695 (2000-10-01), Harris et al.
patent: 6297533 (2001-10-01), Mkhitarian
patent: 6573534 (2003-06-01), Kumar et al.
patent: 2004/0084724 (2004-05-01), Kapels et al.
patent: 2008/0050876 (2008-02-01), Matocha et al.

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