Method of manufacturing semiconductor package and...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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C257S700000, C257S778000, C257S686000, C257SE23001

Reexamination Certificate

active

08030752

ABSTRACT:
A method of manufacturing a semiconductor package may include: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.

REFERENCES:
patent: 6313522 (2001-11-01), Akram et al.
patent: 6365963 (2002-04-01), Shimada
patent: 7365416 (2008-04-01), Kawabata et al.
patent: 7-240496 (1995-09-01), None
patent: 8-250650 (1996-09-01), None
patent: 2005-302922 (2005-10-01), None
patent: 2006-165236 (2006-06-01), None
patent: 10-0754070 (2007-08-01), None
Korean Office Action issued Apr. 29, 2010 in corresponding Korean Patent Application 10-2007-0133242.
Japanese Office Action for corresponding Japanese Patent Application No. 2008-198305 dated Nov. 24, 2010 (3 pgs).

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