Method of manufacturing semiconductor memory device

Details Method of manufacturing semiconductor memory device Method of manufacturing semiconductor memory device

1986-12-18

1987-10-27

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

437 27, 437 52, 437 41, 156657, 1566591, 156662, 357 236, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

047027975

ABSTRACT:
A method of manufacturing a semiconductor device comprises the steps of forming memory cell portions (2, 4, 6, 11) on a p.sup.- -type semiconductor substrate (1), forming a gate insulator film (5) and a gate electrode (3) each having a larger width, by approximately 1 .mu.m, than the original width, ion-implanting p-type impurities utilizing the gate insulator film (5) and the gate electrode (3) as masks, to form p.sup.+ -type regions (120, 121), etching the side walls of the gate insulator film (5) and the gate electrode (3) to the original width and then, ion-implanting n-type impurities utilizing these regions as a mask, to form n.sup.+ -type regions (80, 81), and heat-treating these regions (80, 81, 120, 121), to form regions (80a, 81a, 120a, 121a). The p.sup.+ -type regions (120a, 121a) prevent passage of electrons out of electron-hole pairs induced by alpha rays, to prevent occurrence of soft errors. The p.sup.+ -type regions (120a, 121a) are located inside the n.sup.+ -type regions (80a, 81a), so that operation of a parasitic pnp transistor is not caused.

REFERENCES:
patent: 4597824 (1986-07-01), Shinada et al.
"Alpha-Particle-Induced Soft Error Rate in VLSI Circuits", George A. Sai-Halasz et al, IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 725-731.

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