Method of manufacturing semiconductor devices with titanium...

Details Method of manufacturing semiconductor devices with titanium... Method of manufacturing semiconductor devices with titanium...

2001-12-27

2003-01-14

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S685000, C438S653000, C438S656000, C438S580000

Reexamination Certificate

active

06506676

ABSTRACT:

TECHNICAL FIELD
A method of manufacturing semiconductor devices, and more particularly to, a method of semiconductor devices is disclosed wherein the devices are capable of reducing the threshold voltage (V
th
), by which a metal gate electrode having a dual work-function having a low work-function in a nMOS region and a high work-function in a pMOS region is formed when a surface channel CMOSFET is formed during the process of manufacturing a metal gate, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region.
BACKGROUND
Generally, a silicon oxide film (SiO
2
film) is used as a gate dielectric film of a DRAM device and a logic device in mass-produced, semiconductor devices. As the design rule is scaled down, there is a trend that the thickness of the SiO
2
is reduced to below the range of 25~30 Å which limits tunneling. It is expected that the thickness of a DRAM gate dielectric film of a sub-0.10 &mgr;m technology is in the range of about 30~35 Å and the thickness of a logic device gate dielectric film is in the range of 13~15 Å. If a currently polysilicon gate electrode is continuously employed, however, the components in the thickness of the gate dielectric film, that is electrically increased by the gate poly depletion falls within the range of 3~8 Å, which thus significantly reducing the thickness of an effective gate oxide film (T
eff
) to the approximate range of 15~30 Å.
Therefore, in order to overcome this problem, there has been recent efforts to adopt a high-k dielectric material as the gate dielectric film. Meanwhile, there has been efforts to minimize a poly gate depletion phenomenon by using a metal gate instead of a currently developed polysilicon gate. Also, in case of P
+
poly gate, a lot of research has recently been made since using the metal gate can prevent problems such as boron penetration. In case of the metal gate electrode, a lot of research has been conducted relating to the use of TiN or WN. The work function value is formed toward the valence band in a mid-gap work function since it has a work function in the range of 4.75~4.85 eV.
In case of the surface channel pMOSFET, it could be said that the work function is appropriate. However, in case of nMOSFET, it means that the threshold voltage (V
th
) is almost in the range of 0.8~1.2 V when the channel doping is about 2~5×10
17
/cm
3
. In other words, in this case, a target threshold voltage of 0.3~0.6 V could not be achieved which is required in a high performance device having low-voltage or low-power characteristics. Therefore, in order to obtain a low threshold voltage of about 0.3~0.6 V both in nMOS and pMOS simultaneously, it is preferred that a dual metal electrode is used having the work function value of about 4.2 eV in case of nMOS and having the work function value of about 4.8 eV in case of pMOS.
SUMMARY OF THE DISCLOSURE
A method of manufacturing semiconductor devices which reduces the threshold voltage (V
th
), in a way that a surface channel CMOS device is implemented both in nMOS and pMOS by forming a metal gate electrode having a dual work-function having a low work-function in a nMOS region and a high work-function in a pMOS region, when a surface channel CMOSFET is formed in a meta gate manufacture process.
The disclosed method of semiconductor devices comprises the steps of forming a P-well and a N-well in a semiconductor substrate to define an nMOS region and a pMOS, respectively; forming a first gate insulating film in the nMOS region and a second gate insulating film in, the pMOS region, respectively; forming a first (Ti
x
Al
y
)
1-z
N
z
film on the first gate insulating film and a second (Ti
x
Al
y
)
1-z
N
z
film on the second gate insulating film, respectively; forming a first metal gate electrodes on the first (Ti
x
Al
y
)
1-z
N
z
film and a second metal gate electrodes on the second (Ti
x
Al
y
)
1-z
N
z
film, respectively; and forming a N-type source/drain junction at the semiconductor substrate in the nMOS region and a P-type source/drain junction at the semiconductor substrate in the pMOS region, respectively.
In the above, the first (Ti
x
Al
y
)
1-z
N
z
film has a work function value ranging from about 4.2 to about 4.3 eV, wherein z ranges from about 0.0 to about 0.2. The second (Ti
x
Al
y
)
1-z
N
z
film has the work function value ranging from about 4.8 to about 5.0 eV, wherein z ranges from about 0.3 to about 0.6. Each of the first and second (Ti
x
Al
y
)
1-z
N
z
films is formed with a thickness ranging from about 100 to about 500 Å.


REFERENCES:
patent: 5231306 (1993-07-01), Meikle et al.
patent: 5688722 (1997-11-01), Harrington, III
patent: 6238739 (2001-05-01), Madar et al.
patent: 6287965 (2001-09-01), Kang et al.
patent: 6373111 (2002-04-01), Zheng et al.
patent: 2001/0043453 (2001-11-01), Narwankar et al.
Shew et al., “Effects of RF bias and nitrogen flow rates on the reactive sputtering of TiAIN films”, Thin Solid Films 293, 1997, pp. 212-219.*
Kim et al., “Anti oxidation properties of TiAIN film prepared by plasma assisted CVD and roles of AI”, Thin Solid Film 307, 1997, pp. 113-119.

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