Method of manufacturing semiconductor devices having multi-level

Details Method of manufacturing semiconductor devices having multi-level Method of manufacturing semiconductor devices having multi-level

1997-08-29

2000-03-14

Niebling, John F.

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438680, 438637, 438672, 438675, 438778, 438781, 438783, 438788, 438789, 438790, H01L 100

Patent

active

060372788

ABSTRACT:
Disclosed is a method of manufacturing a semiconductor device aimed at improving reliability of wiring, more particularly, of a via hole when a silicon oxide film formed by a high density plasma CVD process is used as an inter-level dielectric film in an integrated circuit having a multi-level wiring structure. When the multi-level wiring structure is formed on a semiconductor substrate, after underlying wiring is formed, a silicon oxide film is formed on the entire surface of the substrate by a high density plasma CVD process, and heat treated in inert gas or oxygen atmosphere at a temperature of 300.degree. C. or more but 500.degree. C. or less for 10 minutes or more. Excess hygrogen incorporated in the silicon oxide during the CVD process is removed by the above heat treatment. Subsequently, via holes are opened, and upper wiring is formed.

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Dr. W.G.M. van den Hoek, et al., "A new high density plasma source for void free dielectric gap fill", pp. 195-200, Novellus Systems, Inc.
B.M. Somero et al., "A modular in-situ integration scheme for deep submicron CMOS logic and ASIC applications", pp. 28-34, VMIC Conferences, Jun. 8-9, 1993.
Stephan E. Lassig et al., "Dielectric properties of SiO.sub.2 formed by biased ECR CVD", pp. 122-124, VMIC Conference Jun. 8-9, 1993.

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