Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-06-23
2003-10-14
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S255000, C438S565000, C438S566000, C438S396000
Reexamination Certificate
active
06632721
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor device and a method of manufacture thereof; in particular, the invention relates to a technique effective when adapted for a semiconductor device having a DRAM (Dynamic Random Access Memory).
BACKGROUND OF THE INVENTION
As a DRAM structure for achieving higher integration, a Capacitor Over Bitline (COB) structure is conventionally known, wherein a capacitor is disposed over a bit line, a lower electrode (storage electrode) of the capacitor disposed over a bit line is processed into a cylindrical shape, and a capacitative insulating film and an upper electrode (plate electrode) are formed on the lower electrode. The surface area of the lower electrode is enlarged by processing the lower electrode into a cylindrical shape, whereby a reduction in the accumulated charge amount (Cs) of the capacitor caused by the miniaturization of a memory cell can be compensated for. In a memory cell having a COB structure, it is thus inevitable to three-dimensionally form a capacitor structure in order to secure operation reliability as a semiconductor storage device.
However, it has been difficult to secure the necessary capacitance (accumulated charge amount) even in a recent semiconductor device which has been integrated by three-dimensional formation of its capacitor structure, particularly for versions of a DRAM on and after those corresponding to 256 Mbit (mega-bit).
As a technique for further enlarging the area of an electrode, there is a technique using a so-called HSG (Hemispherical Silicon Grain) structure, that is, a technique for forming minute unevenness on the silicon surface on which the lower electrode is formed to provide a roughened surface. According to this technique, the surface area can be enlarged substantially without increasing the size of the lower electrode.
SUMMARY OF THE INVENTION
The above-described technique for an HSG structure is however accompanied with the following problems, which are not greatly known, but were discovered only by the present inventors.
Adoption of an HSG structure for a lower electrode makes it possible to enlarge the physical surface area of the lower electrode, but it is accompanied with the problem that an increase in the accumulated charge amount in proportion to the surface enlargement is not always possible. In particular, the problem appears eminently when the lower electrode made of n-type silicon is biased positive toward an upper electrode. This is presumed to be caused by the formation of a depletion layer (by appearance of depletion) on the interface of the lower electrode in contact with a capacitor insulating film. More specifically, adoption of an HSG structure for a lower electrode inevitably requires adoption of silicon as a raw material for it. When a silicon material is employed as a conductor, a large amount of impurities must be introduced. When activated impurities are introduced in a sufficient amount, depletion is suppressed. When the introduced amount of impurities is small or impurities introduced in a large amount are not activated, a depletion layer is formed in the silicon. Since this depletion layer is electrically insulating, it acts like a capacitor insulating film and the apparent thickness of the capacitor insulating film seems to show an increase. This leads to a decrease in the capacitance value of the capacitor, resulting in an increase in the accumulative charge amount which is not proportional to an increase in the surface area of the lower electrode. The decrease in the capacitance value of the capacitor (capacitive loss) reaches at least 30% in terms of a depletion ratio, and such a decrease undesirably becomes a large factor for inhibiting an improvement of refresh properties of the DRAM, thereby inhibiting an improvement of the DRAM performance. In this specification, the depletion ratio is defined as (1−C
−
/C
+
), wherein C stands for a capacitance value when a capacitor is biased toward
−
1V, and C
+
stands for a capacitance value when a capacitor is biased toward
−
1V.
As means for avoiding depletion, introduction of impurities in an amount sufficient for compensating for inactivated impurities can be presumed. In order to form an HSG structure, however, it is necessary to subject an amorphous silicon film to predetermined heat treatment, thereby causing solid-phase growth of it into polycrystalline hemispherical crystals. It is needless to say that heat treating conditions (temperature, time, atmosphere, or the like) take part in the growth of crystals from the amorphous state. In addition, an amount of impurities contained in the amorphous silicon, which is a starting material, also takes part in the crystal growth. When a large amount of impurities is contained in the amorphous silicon film, crystallization of amorphous silicon is accelerated excessively, whereby granular silicon (hemispherical crystal) of a sufficient size cannot be formed. The amount of the impurities contained in advance in the amorphous silicon film must therefore be limited and this request for limitation in the amount of impurities is inconsistent with means for suppressing depletion.
Even if the amount of impurities is relatively small so as not to cause a problem in the formation of granular silicon, depletion can be suppressed if these impurities have been sufficiently activated. In other words, it is presumed that depletion can be effectively controlled if impurities contained in the silicon film (lower electrode) after formation of hemispherical crystals have been sufficiently activated (a large portion of impurities contained in the film has been activated). The activation of impurities in silicon however requires heat treatment at a high temperature or for long hours (ex. annealing at a temperature not lower than 800° C. or for a time not shorter than 20 minutes). The following problem occurs when the lower electrode is subjected to such high or long heat treatment. When a COB structure is adopted, a capacitor is formed after formation of a bit line. A first interconnection layer of the peripheral circuit is formed simultaneously with the bit line so that a joint part of the first interconnection layer and substrate in the peripheral circuit (ex. source and drain of MISFET of the peripheral circuit) has already been formed in the capacitor-forming stage. At this joint part, a silicide film such as titanium silicide is formed for decreasing the contact resistance. However, this silicide film is poor in heat resistance so that the heat treatment temperature after formation of the first interconnection layer is limited to a low temperature range within the heat resistance of the silicide film. It is therefore impossible to heat-treat the lower electrode of the capacitor at high temperatures for activation of impurities.
Although attention is paid only to the joint part between the first interconnection layer and substrate, high temperature heat treatment is also unsuited for all the members that have already been formed and are poor in heat resistance, for example, an impurity region formed on a semiconductor substrate. In a highly-integrated semiconductor device, impurity diffusion layers (source drain, etc.) are formed while their position and depth are controlled precisely. By the heat treatment at a high temperature or for long hours, impurities in the impurity diffusion layer, which has been formed precisely, are re-diffused, whereby its structure is changed. It is needless to say that such a change puts the original design out of order and adversely affects the properties of the device. In addition, when a p
+
gate structure having a boron-implanted gate electrode (polycrystalline silicon film) is adopted, boron is diffused (leaked) by the heat treatment and diffused boron reaches a channel region, which changes the threshold value of the MISFET. This also becomes a factor for deteriorating the properties of the device, thereby lowering the reliability of the semiconductor device.
With the miniaturizatio
Fujisaki Yoshihisa
Iijima Shinpei
Kuroda Jun
Miki Hiroshi
Yamaguchi Kenichi
Meier Stephen D.
Novacek Christy
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