Method of manufacturing semiconductor devices

Details Method of manufacturing semiconductor devices Method of manufacturing semiconductor devices

1997-05-23

2000-11-28

Bowers, Charles

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438624, 438902, H01L 2144

Patent

active

061535427

ABSTRACT:
In a method of manufacturing a semiconductor device, a first plasma insulating film having a thickness of 0.1 .mu.m or more is formed on the semiconductor substrate with lower-surface wirings thereon. The semiconductor substrate is moved into a pressure-reduced CVD device, and then an SiH.sub.4 gas and H.sub.2 O.sub.2 are supplied into the pressure-reduced CVD device to react them to each other in a vacuum of 650 Pa or less within the temperature range of -10.degree. C. to +10.degree. C. to form a reflow SiO.sub.2 film having a thickness of 0.4 .mu.m to 1.4 .mu.m on the semiconductor substrate. The semiconductor substrate is put in a vacuum of 6.5 pascal for 30 seconds or more. Thereafter, the semiconductor substrate is put at a high temperature of 300.degree. C. to 450.degree. C. for 120 to 600 seconds. A second plasma insulating film having a thickness of 0.3 .mu.m or more and serving as a cap film is formed on the semiconductor substrate. The crack resistance of the reflow insulating film formed in the above steps is improved, and the flatness of the reflow insulating film is improved.

REFERENCES:
patent: 5190792 (1993-03-01), Blum et al.
patent: 5314724 (1994-05-01), Tsukun et al.
patent: 5683940 (1997-11-01), Yahiro
patent: 5700720 (1997-12-01), Hashimoto
Dobson, C.D. et al. "Advanced SiO2 Planarization using silane and H202", Semiconductor International, Dec. 1994, vol. 17, No. 14, pp. 85-86.
Matsuura M. et al., "Novel Self-Planarization CVD Oxide for Interlayer Dielectric Applications", International Electron Devices Meeting 1994. Technical digest (cat. No. 94CH35706) New York, NY: IEEE, 1994, p. 117-20. ISBN: 0-7803-2111-1.
C.D. Dobson, "Advanced SiO.sub.2 Planarization Using Silane and H.sub.2 0.sub.2 ", Semiconductor International, Dec. 1994, pp. 85-88.
M. Matsuura et al., "Novel Self-planarizing CVD Oxide for Interlayer Dielectric Applications", IEEE, 1994, pp. 117-120.

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