Method of manufacturing semiconductor devices

Details Method of manufacturing semiconductor devices Method of manufacturing semiconductor devices

1986-05-21

1987-07-07

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29576W, 29591, 148 15, 148187, 156644, 156646, 156653, 156657, 156662, 1566611, 427 93, 357 34, 357 59, 357 91, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

046785370

ABSTRACT:
To reduce the parasitic capacitance due to the graft base area in a transistor device and to miniaturize the device, the graft base area is connected to a conductive layer to be connected to the base electrode through a minute gap of about 1,000 .ANG.. This minute gap can be formed by leaving an oxide resistant layer (1,000 .ANG.) at the side wall portion of the conductive layer of which peripheral portion is perpendicular to the surface of the base area by applying an isotropic etching technique and by removing the remaining oxide resistant layer on the basis of selective etching technique, after thermal oxidation of the device with masking the side wall portion by the remaining oxide resistant layer.

REFERENCES:
patent: 4239559 (1980-12-01), Ito

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