Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
1996-11-05
2001-11-13
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S369000, C438S364000, C438S309000, C438S378000
Reexamination Certificate
active
06316324
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
FIGS. 14A
to
14
D are views for explaining a method of manufacturing a vertical NPN transistor as an example of a semiconductor device.
First, as shown in
FIGS. 14A and 14B
, selective ion implantation or thermal diffusion using a P-type impurity (e.g., boron B
+
) is performed to form a base region
100
. As shown in
FIGS. 14B and 14C
, an emitter region
101
is formed by selective ion implantation or thermal diffusion using an N-type impurity (e.g., arsenic As
+
). After this formation of the emitter region
101
, a P-type impurity (e.g., boron B
+
) is selectively ion-implanted or thermally diffused again in a contact region of the base region
100
to form an inner base region
102
, as shown in
FIGS. 14C and 14D
.
When the vertical NPN transistor is to be formed by the above conventional manufacturing method, however, a patterning (to be referred to as lithography hereinafter) step using a photosensitive resin (to be referred to as a resist hereinafter) must be performed when the base region
100
, emitter region
101
, and inner base region
102
are formed, respectively. As a result, the manufacturing time and cost are increased. In addition, an alignment shift in lithography must be taken into consideration, which limits a reduction in device size.
Such a problem similarly arises in forming N- and P-well layers, in forming N- and P-buried layers, and in forming N- and P-diffusion layers.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device which can shorten the manufacturing time and reduce the manufacturing cost by simplifying the manufacturing method in the prior art, and can reduce the size of a device pattern.
To achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the step of doping an N-type impurity via a selective region formed a semiconductor substrate by lithography, the step of doping a P-type impurity in the semiconductor substrate subsequent to the doping step without forming a selective region by lithography, and the step of self-aligningly forming an N-diffusion layer and a P-diffusion layer by performing wet oxidation with respect to the semiconductor substrate in which the N-type impurity and the P-type impurity are doped.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
FIGS. 1A
to ID are views for explaining a method of manufacturing a vertical NPN transistor according to the first embodiment of the present invention;
FIGS. 2A
to
2
C are graphs showing the simulation results of a base region, an emitter region, and a collector region when the first embodiment is carried out;
FIGS. 3A
to
3
C are graphs showing the simulation results of a base region, an emitter region, and a collector region which are formed by the prior art;
FIGS. 4A
to
4
D are views for explaining a method of manufacturing a vertical NPN transistor according to the second embodiment of the present invention;
FIGS. 5A
to
5
C are views for explaining a method of manufacturing a CMOS transistor according to the third embodiment of the present invention;
FIGS. 6A and 6B
are a graph and a table respectively showing a simulation result immediately below the gate of an NMOS in the prior art;
FIGS. 7A and 7B
are a graph and a table respectively showing a simulation result immediately below the drain/source of the NMOS in the prior art;
FIGS. 8A and 8B
are a graph and a table respectively showing a simulation result immediately below the drain/source of an NMOS in the third embodiment;
FIGS. 9A and 9B
are a graph and a table respectively showing a simulation result immediately below the gate of a PMOS in the prior art;
FIGS. 10A and 10B
are a graph and a table respectively showing a simulation result immediately below the drain/source of the PMOS in the prior art;
FIGS. 11A and 11B
are a graph and a table respectively showing a simulation result immediately below the drain/source of a PMOS in the third embodiment;
FIGS. 12A
to
12
D are views for explaining a method of manufacturing a well layer according to the fourth embodiment of the present invention;
FIGS. 13A
to
13
D are views for explaining a method of manufacturing a buried layer according to the fifth embodiment of the present invention;
FIGS. 14A
to
14
D are views for explaining a method of manufacturing a vertical NPN transistor when the prior art is used; and
FIG. 15A
is a table showing the acceleration voltage and the ion dose used in the simulation in the first embodiment, while
FIG. 15B
is a table showing the acceleration voltage and the ion dose in the prior art.
REFERENCES:
patent: 5071778 (1991-12-01), Solheim
patent: 5424572 (1995-06-01), Solheim
patent: 5439833 (1995-08-01), Herbert et al.
patent: 5443994 (1995-08-01), Solheim
patent: 5466615 (1995-11-01), Tsai
patent: 5466960 (1995-11-01), Ilderem et al.
S. Wolf, Silicon Processing for the VLSI Era, V1-V2, pp. 198-219 and 510-525, respectively, 1990.*
S.M. Sze VLSI Technology, 2nd edition, pp. 121-125, 1988.
Anai Yasuko
Dohi Yasuhiro
Honna Katsu
Kyuho Takashi
Sato Kazuhiro
Bowers Charles
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hawranek Scott J.
Kabushiki Kaisha Toshiba
LandOfFree
Method of manufacturing semiconductor device without forming... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing semiconductor device without forming..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor device without forming... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2618136