Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-04-07
2001-11-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S723000, C438S737000, C438S738000, C438S743000
Reexamination Certificate
active
06319844
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device. It particularly relates to a manufacturing method of a semiconductor device with varying widths of interconnect layers; wherein, an HSQ layer is used as the interlayer insulating film and the bottom of the via hole that reaches the concerned interconnect layer exactly ends only at the upper surface of the concerned interconnect layer.
2. Related Arts
Conventionally, it is known that the working speed of a semiconductor device decreases as the product (RC) of the wiring resistance (R) and the parasitic capacitance (C) between interconnects increases; Meanwhile, the parasitic capacitance (C) between interconnects increases in an inverse proportion to the distance between interconnects. Therefore, in order to improve the working speed of the semiconductor device, it is important to decrease the parasitic capacitance between interconnects.
From this viewpoint, a technique for forming an insulating layer with a low dielectric constant between densely positioned interconnects is widely used. The HSQ (hydrogen silsesquioxane) layer is an example of this type of low dielectric constant insulating layer. An example of an etching technique using this HSQ layer will now be described using
FIGS. 1A and 1B
and
FIGS. 2A and 2B
. Namely, as shown in
FIG. 1A
, a metal interconnect
202
with a TiN/Ti/Al—Cu/TiN stucture and a total thickness of approximately 600 nm is formed on top of interlayer base film
201
made of a plasma SiO
2
film. On top of that, an HSQ layer
203
of approximately 400 nm is spin-coated and then let to cure.
Nest, a second plasma SiO
2
layer
204
of approximately 1400 nm is formed and smoothed out using chemical/mechanical polishing (hereafter called CMP) resulting in an insulating layer of 700 nm on the metal interconnects.
Next, as shown in
FIG. 1B
, a photoresist is deposited and patterned so as to assist in forming a thru hole. Afterwards, an oxidized film dry etching system with its etching parameters being optimally set so as for the interlayer films
204
and
203
on top of the smaller area of a metal interconnect to be partially etched off, etches the P—SiO
2
/HSQ films using a C
4
F
8
/Ar/O
2
/CO gas chemistry. As a result, the HSQ layer on top of the smaller area of a metal interconnect is successfully etched off, but the HSQ layer above the larger 1 nm
2
area of metal interconnect is left partially un-etched, as shown in FIG.
2
A.
In another example, if O
2
gas is increased in order to improve the effectiveness of the etching on the larger area of metal interconnects, then the thru hole formed above the larger area of metal interconnects is able to reach the surface. However, the small thru hole above the smaller area of metal interconnects ends up being over-etched. Besides, since the etch selectivity to the TiN cannot be sufficiently provided, a large chunk of the upper portion of the smaller area of the metal interconnect is removed, as shown in FIG.
2
B. As a result, the expected resistance cannot be provided, thereby making it difficult to stop the etching on top of the TiN layer.
In other words, since the HSQ layer coated on the large area of the metal interconnect is thick, but the one coated on the smaller area is then, and also since a high etch selectivity of the P—SiO
2
to the HSQ is provided, the etching rate decreases in the very small hole in the HSQ layer. Therefore the etching cannot go all the way through the part where the HSQ is thick. This is because the processing of the very small holes in the HSQ leads to hydrogen developing inside the HSQ layer during etching, and the fluorine part of the etchant is then accordingly released as a HF gas, which causes the etching to cease.
Furthermore, when the etching process is used to dig a hole in the thick HSQ layer, it is difficult to achieve etching that ends exactly on top of the TiN layer. This is because the etching time is increased when etching a thick HSQ layer, but this also results in the over-etching of the TiN metal where the HSQ is thin.
For example, according to Japanese Patent Application Laid-open No. Hei 7-226531, the usage of mesa photodetectors in order to reduce the parasitic capacitance originating from the electrodes or pads is described, but the structure with HSQ layers is not described.
Furthermore, Japanese Patent No. 2560637 describes, with the purpose of reducing the parasitic capacitance in order to increase the speed of the FETs, techniques to set up spacers that have a lower dielectric constant than the oxidized silicon on the surface of the gate electrode side. However, semiconductor devices using HSQ layers are not described.
SUMMARY OF THE INVENTION
Therefore, the purpose of the present invention is to improve the defects in the above-mentioned techniques, and provide a method of manufacturing a semiconductor device in which the bottom of each via hole where plugs connect to interconnect layers ends exactly at the surface of said interconnect layers.
According to an aspect of the present invention, a method of fabricating a semiconductor device, which is comprised of differing top surface areas of respective interconnect layers, a first insulation layer with a low dielectric constant that is deposited over said differing top surface areas of the respective interconnect layers, and a second insulation layer that is deposited on top of said first insulation layer, is provided and is comprised of the step of etching both parts of said first and said second insulation layer on top of said differing top surface areas of the respective interconnect layers, successively under the condition such that the etch selectivity of said first insulation layer to the second insulation layer is equal to almost 1, so as to make via holes. An example of this method is shown in
FIGS. 3A
to
3
D.
REFERENCES:
patent: 4668338 (1987-05-01), Maydan et al.
patent: 5378318 (1995-01-01), Weling et al.
patent: 6022810 (2000-02-01), Kusumi et al.
patent: 6083845 (2000-07-01), Yang et al.
patent: 6103137 (2000-08-01), Park
patent: 6133137 (2000-10-01), Usami
patent: 0 266 522 (1987-09-01), None
patent: 7-226531 (1995-08-01), None
patent: 2560637 (1996-09-01), None
Miyamoto Hidenobu
Usami Tatsuya
Malsawma Lex H.
NEC Corporation
Smith Matthew
Young & Thompson
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