Method of manufacturing semiconductor device with silicide...

Details Method of manufacturing semiconductor device with silicide... Method of manufacturing semiconductor device with silicide...

2006-11-17

2010-12-28

Purvis, Sue (Department: 2826)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257SE21203, C257SE21622

Reexamination Certificate

active

07858524

ABSTRACT:
A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and a silicide gate electrode of a p-type MISFET formed on the gate insulation film and having a thickness smaller than that of the silicide gate electrode of the n-type MISFET, the silicide gate electrode of the p-type MISFET having a ratio of metal content higher than that of the silicide gate electrode of the n-type MISFET.

REFERENCES:
patent: 6909156 (2005-06-01), Aoyama
patent: 2004/0084734 (2004-05-01), Matsuo
patent: 2005/0199963 (2005-09-01), Aoyama
patent: 2005/0285206 (2005-12-01), Kadoshima et al.
Kedzierski et al., Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS), IEDM Tech Dig. 315 (2003), 4 pages.
Kedzierski et al., “Metal-gate Fin FET and fully-depleted SOI devices using total gate silicidation,” IEDM Tech Dig. 247 (2002), 4 pages.
K. Takahashi et al., “Dual Workfunction Ni-Silicide/HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45nm-node LSTP and LOP Devices,” IEDM Technical Digest, pp. 91-94 (2004).
T. Aoyama et al., Proposal of New HfSiON CMOS Fabrication Process (HAMDAMA) for Low Standby Power Device, IEDM Technical Digest, pp. 95-98 (2004).

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