Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2002-12-19
2004-08-24
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S974000
Reexamination Certificate
active
06780737
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices, and more particularly to a method of manufacturing semiconductor devices with buried conductive lines.
2. Description of the Related Art
Modern semiconductor devices are designed and fabricated toward a trend of size minimization so that more and more devices can be packed in a chip with a limited area. In order to shrink the device sizes of these semiconductor devices and pack these semiconductor devices into one chip as more as possible, various conventional processes of fabricating these semiconductor devices have been improved or even replaced with new processes to overcome many nature limits. Semiconductor devices such as logic devices and memory devices particularly have the necessaries of size decrease and integration increase so that they can operate more powerfully and store more data.
As the density of these semiconductor devices continually increases, the multilevel interconnect structures of these semiconductor devices also have more and more levels. Meanwhile, the problems of the process window decrease and the reducing of planarization are also raised.
FIG. 1
shows a cross-sectional diagram of conventional dynamic random access memory (DRAM) devices whose capacitors are not shown. A substrate
100
, gate electrodes
102
a
and
102
b,
dielectric layers or interlevel dielectric (ILD) layers
104
and
108
, a contact
106
, a bit line
107
, contacts
110
a
and
110
b,
and metal lead lines
112
a
and
112
b a
re also shown in FIG.
1
. The contact
106
and the bit line
107
as well as the contacts
110
a
and
110
b,
and the metal lead lines
112
a
and
112
b
are limits of integration increase and render the planarization of this integrated circuit degrading.
In view of the drawbacks mentioned with the prior art process, there is a continued need to develop new and improved processes that overcome the disadvantages associated with prior art processes. The requirements of this invention are that it solves the problems mentioned above.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a simplified process of forming contacts and lead lines of semiconductor devices.
It is another object of this invention to increase the integration and the die density of semiconductor devices and decrease the overhead of the semiconductor devices.
It is a further object of this invention to improve planarization of semiconductor devices and increase process window of the semiconductor devices.
To achieve these objects, and in accordance with the purpose of the invention, the invention uses a method comprising: providing a substrate; forming a trench in said substrate to form a isolation region therein and define active regions; forming a patterned mask layer over said substrate to expose adjacent active regions; and implanting ions into said substrate with a tilt angle to form a buried conductive line therein connecting adjacent active regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 6611037 (2003-08-01), Rhodes
patent: 6620698 (2003-09-01), Chen et al.
patent: 2002/0039821 (2002-04-01), Wolstenholme
Coleman W. David
Macronix International Co. Ltd.
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