Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-01-25
2002-07-16
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000
Reexamination Certificate
active
06420191
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of DRAM (Dynamic Random Access Memory) including a capacitor dielectric film made of a material having a large dielectric constant and a manufacturing method therefor.
2. Related Background Art
Hitherto, DRAM has been widely employed as one of semiconductor devices permitting information to be input and output randomly. In general, DRAM has a memory cell array portion serving as a storage region for storing a multiplicity of information items to be stored and peripheral circuit portions required to input and output information to and from outside.
FIG. 21
is a block diagram showing the structure of a general DRAM.
As shown in
FIG. 21
, a DRAM
150
has a memory cell array
151
for storing information, a row-and-column address buffer
152
for receiving, from outside, an address signal for selecting a memory cell forming a unit storage circuit, a row decoder
153
and a column decoder
154
which decode the address signal to appoint a memory cell, a sense refresh amplifier
155
for amplifying and reading signals stored in the appointed memory cell, a data-in buffer
156
and a data-out buffer
157
for inputting and outputting data, and a clock generator
158
for generating a clock signal.
The memory cell array
151
having a large area on the semiconductor chip has a plurality of memory cells arranged to store unit storage information and formed into a matrix configuration. In general, one memory cell is composed of one MOS (Metal Oxide semiconductor) transistor and one capacitor connected to the MOS transistor. A memory cell of the foregoing type is called a 1-transistor and 1-capacitor type memory cell. Since a memory cell of this type has a simple structure, the degree of integration of the memory cell array
151
can easily be raised. Therefore, the foregoing memory cells have been employed widely in DRAM having large capacities.
The memory cells of the DRAM can be classified into some types depending upon the structure of the capacitor. Capacitors of a type called a stacked capacitor are included in the capacitors of the memory cells. The stacked capacitor has a structure such that the major portion of the capacitor is extended to the position above the gate electrode and the field oxide film so that the areas of the opposite portions of the electrodes of the capacitors are enlarged.
Since the stacked capacitor has the foregoing characteristic, a required capacity of the capacitor can easily be obtained even if the device is fined due to raising of the degree of integration of the semiconductor device. As a result, stacked capacitors have been employed widely in the trend of the degree of integration of the semiconductor devices being raised. However, if the stacked capacitor is employed in a further fined device, example, a 256 M bit DRAM, a predetermined capacity of the capacitor cannot easily be obtained with the foregoing stacked capacitor.
Accordingly, the capacity of the capacitor has been enlarged by performing an attempt such that a dielectric film, for example, PZT (lead zirconate titanate) having a large dielectric constant, is employed as the dielectric film for the capacitor.
FIG. 22
shows an example of a DRAM comprising a dielectric film for a capacitor, the dielectric film being made of a material, such as, PZT, having a large dielectric constant.
As shown in
FIG. 22
, a P-type semiconductor substrate
101
has a major surface in which a field oxide film
102
is formed in a device separated region of the major surface. A device region on the major surface of the semiconductor substrate
101
has transfer gate transistors
103
a
and
103
b
formed thereon.
The transfer gate transistor
103
a
has a gate electrode
104
b
formed, through a gate insulating film
105
, on a channel region
121
between N-type impurity regions
106
c
and
106
a
formed apart from each other on the major surface of the semiconductor substrate
101
to serve as source and drain regions.
The transfer gate transistor
103
b
has a gate electrode
104
c
formed, through the gate insulating film
105
, on the N-type impurity regions
106
a
and
106
b
, serving as the source and drain regions, and the channel region
121
between the impurity regions
106
a
and
106
b.
On the field oxide film
102
, there is extended a gate electrode
104
d
of another transfer gate transistor. An oxide film
107
is formed to cover the gate electrodes
104
b
,
104
c
and
104
d
. On the impurity region
106
a
, there is formed a buried bit line
108
so as to be electrically connected to the impurity region
106
a
. An insulating layer
109
is formed to cover the buried bit line
108
.
A first interlayer insulating film
110
is formed to cover the insulating film
109
and the oxide film
107
. The top surface of the first interlayer insulating film
110
is flattened. The first interlayer insulating film
110
has a contact hole
110
a
in a portion above the impurity region
106
b.
A plug
111
, electrically connected to the impurity region
106
b
, is formed in the contact hole
110
a
. A lower electrode
114
of the capacitor, made of platinum or the like, is formed between the top surface of the plug
111
and that of the first interlayer insulating film
110
.
A capacitor dielectric film
115
is formed to cover the lower electrode
114
of the capacitor. The capacitor dielectric film
115
is made of PZT, SrTiO
3
or the like. An upper electrode
116
of the capacitor is formed to cover the capacitor dielectric film
115
. The upper electrode
116
of the capacitor is, in general, made of platinum.
A second interlayer insulating film
117
is formed to cover the upper electrode
116
of the capacitor. The top surface of the second interlayer insulating film
117
is flattened. A first aluminum line layer
118
is formed above the second interlayer insulating film
117
while being apart from the same. A protective film
119
is formed to cover the first aluminum line layer
118
. An aluminum line layer
120
is formed on the protective film
119
.
The lower electrode
114
of the capacitor, the capacitor dielectric film
115
and the upper electrode
116
of the capacitor form a capacitor
160
.
However, the conventional DRAM suffers from the following problems: the conventional DRAM has included the platinum films to form the lower electrode of the capacitor, electrically connected to the major surface of the semiconductor substrate through the opening in the interlayer insulating film, and the upper electrode of the capacitor formed on the capacitor dielectric film.
1) Although the platinum film has an advantage that it does not easily form a reactive layer in the interface with the dielectric film, the platinum film has a poor reactivity and, therefore, it cannot easily be processed.
2) Known materials except platinum, for example, ruthenium, iridium and the like, for forming the electrode, have a problem of a poor adherence with the silicon oxide film serving as the interlayer insulating film when the foregoing material is formed into a thin film.
3) When the capacitor dielectric film is formed, oxidation of the silicon plug taking place due to oxidation of the foregoing material for forming the electrode cannot be prevented. Thus, the contact resistance will be enlarged excessively and the capacitance is reduced undesirably.
4) Moreover, if the material for forming the electrode, such as ruthenium or iridium, is oxidized, the surface of the material is roughened unintentionally, thus raising a problem in that a leakage current is enlarged excessively. In a case where a metal electrode, made of ruthenium or iridium, is formed and then the metal electrode is subjected to heat treatment at high temperature, the surface of the metal electrode is sometimes roughened though the atmosphere is not the oxidizing atmosphere. Thus, there arises a problem in that the leakage current is enlarged excessive
Horikawa Tsuyoshi
Kuroiwa Takeharu
Makita Tetsuro
Mikami Noboru
Shibano Teruo
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