Method of manufacturing semiconductor device utilizing a lift-of

Details Method of manufacturing semiconductor device utilizing a lift-of Method of manufacturing semiconductor device utilizing a lift-of

1980-09-03

1983-02-01

Massie, Jerome W.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156656, 156657, 1566591, 156662, 430314, H01L 21283, H01L 21308

Patent

active

043714234

ABSTRACT:
A method of manufacturing a semiconductor device comprising a step of covering a principal surface of a semiconductor substrate having semiconductor regions formed therein and at least partly provided with a silicon oxide film with a cover film having an etching characteristic different from that of the oxide film, a step of forming a first deposition layer having a higher etching speed than that of the cover layer on the cover layer, a step of forming a second deposition layer having a lower etching speed than that of the first deposition layer on the first deposition layer, a step of etching away portions of the second and first deposition layers and cover layer corresponding to a wiring pattern in succession, a step of etching the exposed portions of the silicon oxide film with the cover layer having the openings as a mask to thereby form contact holes with respect to the semiconductor substrate, and a step of forming wiring leads by depositing a wiring metal and etching away the first deposition layer and thus lifting off the second deposition layer and wiring metal portions thereon.

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Horng et al., "IBM Technical Disclosure Bulletin "Narrow Base . . . Structure", vol. 22, #9, (2/80), pp. 4054-4116.
Gegenworth et al., "Capped . . . Devices" IBM Technical Disclosure Bulletin, vol. 15, #11, (4/73), pp. 3538-3539.
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"Two Layered, Highly Packed Interconnection Metallization by a Lift-Off Process Utilizing PIO", Semiconductor Transistor Research Institute, SSD 78-65, pp. 33-40, Y. Homma et al.

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