Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-09-08
2001-10-23
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S030000
Reexamination Certificate
active
06306693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device comprising a thin film transistor (referred to as “TFT” hereinafter), a method of manufacturing an active matrix substrate, and an electrooptic device comprising the active matrix substrate. More specifically, the present invention relates to a technique for forming LDD structure or offset gate structure TFT.
2. Description of the Related Art
of various types of semiconductor devices, an active matrix substrate with a built-in driving circuit of an electrooptic device such as a liquid crystal display device or the like, or an active matrix substrate of a current drive control-type display device comprises TFT as a pixel switching element or a switching element which constitutes a driving circuit. In order to improve the electric strength of TFT or reduce an off-leak current in an active matrix substrate, a technique is frequently used for imparting an offset gate structure or LDD structure to TFT.
Such a LDD structure or offset structure TFT is conventionally produced by the following method.
First, as shown in
FIG. 10B
, an under protecting film (not shown) and a silicon film
1012
(semiconductor film) are formed in turn on a substrate
11
shown in FIG.
10
A. Then, as shown in
FIG. 10C
, the silicon film
1012
is patterned to form an island-like silicon film
1012
. Next, as shown in
FIG. 10D
, a gate insulating film
1013
is formed on the surface of the silicon film
1012
, and then a conductive film is formed on the surface thereof, and patterned to form a gate electrode
1014
.
In producing LDD structure N-type (first conduction type) TFT, as shown in
FIG. 10E
, low concentration N-type (low concentration first conduction type) impurities such as phosphorus ions or the like are next introduced into the silicon film
1012
by using the gate electrode
1014
as a mask. As a result, low-concentration n-type regions
1151
are formed in the silicon film
1012
in self alignment with the gate electrode
1014
, the portion in which the impurities are not introduced serving as a channel forming region
1017
.
Next, as shown in
FIG. 10F
, a resist mask
1055
is formed to cover a region slightly wider than the gate electrode
1014
, and then as shown in
FIG. 10G
, high-concentration N-type (high concentration first conduction type) impurities such as phosphorus ions are introduced into the silicon film
1012
.
As a result, a portion of each of the low-concentration N-type regions
1151
becomes a high-concentration N-type region
1152
.
Next, as shown in
FIG. 10H
, an interlayer insulating film
1018
is formed on the surface side of the gate electrode
1014
, a contact hole is formed in the interlayer insulating film
1018
, and then source and drain electrodes
1051
and
1052
are formed to be electrically connected to the high-concentration N-type regions
1152
through the contact hole of the interlayer insulating film
1018
.
The thus-constructed TFT
1010
has the LDD structure in which portions of the source drain regions
1015
to which the source and drain electrodes
1051
and
1052
are electrically connected are the high-concentration N-type regions
1152
, portions confronted to each other with the gate insulating film
1013
provided therebetween at the ends of the gate electrodes
1015
being the low-concentration regions
1151
.
The step of introducing the low-concentration n-type impurities shown in
FIG. 10E
is omitted to obtain TFT
1010
having the offset gate structure in which portions corresponding to the low-concentration n-type regions
1151
have the same impurity concentration as the channel forming region.
However, in the conventional method of producing the LDD structure or offset gate structure TFT
1010
, the LDD length or offset length is defined by the distance between an end of the resist mask
1055
and an end of the gate electrode
1014
, and thus even when the forming position of the resist mask
1055
is slightly deviated from the gate electrode
1014
, this deviation causes the problem of bringing about a variation in the LDD length or offset length.
Therefore, various studies are carried out as to how to manufacture TFT without causing a variation in the LDD length or offset length. However, in many cases, not only N-type TFT
1010
but also P-type TFT are generally formed on the same substrate, and many steps are required for forming such different conduction type TFTS. It is thus undesirable to complicate the manufacturing process even for suppressing a variation in the LDD length or offset length.
Furthermore, besides the TFTs, a capacitor is also formed on the same substrate in some cases. In this capacitor, a semiconductor region formed at the same time as source-drain regions of TFTs serves as an electrode, other electrodes being formed at the same time as gate electrodes of TFTs. Therefore, there is a restriction that impurities must be introduced into a semiconductor film located on the lower layer side of the gate electrode before the gate electrode is formed, thereby causing difficulties in suppressing a variation in the LDD length or offset length without complicating the manufacturing process under the restriction.
Therefore, under the present circumstances, in a method of manufacturing a semiconductor device in which different conduction type TFTs are formed on the same substrate, or a method of manufacturing a semiconductor device in which the capacitor is also formed on the same substrate as these TFTS, a variation in the LDD length or offset length of TFT cannot be sufficiently prevented.
Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which is capable of suppressing a variation in the LDD length or offset length of TFT by a small number of steps for forming different conduction type TFTs on the same substrate, and decreasing defects due to a pattern residue in a wiring region or the like, a method of manufacturing an active matrix substrate, and an electrooptic device comprising the active matrix substrate.
Another object of the present invention is to provide a method of manufacturing a semiconductor device which is capable of decreasing defects due to a pattern residue in a wiring region or a capacitor forming region, a method of manufacturing an active matrix substrate, and an electrooptic device comprising the active matrix substrate.
A further object of the present invention is to provide a method of manufacturing a semiconductor device which is capable of producing different conduction type TFTs and a capacitor by a small number of steps while suppressing a variation in the LDD length of offset length of TFT, a method of manufacturing an active matrix substrate, and an electrooptic device comprising the active matrix substrate.
SUMMARY OF THE INVENTION
In order to solve the above problems, the present invention provides a method of manufacturing a semiconductor device in which LDD structure or offset gate structure first conduction type TFT and self-aligned structure second conduction type TFT are formed from a semiconductor film formed on a substrate, the method comprising the first gate insulating film forming step of forming a first gate insulating film on the surface of the semiconductor film, the first gate electrode forming step of forming a gate electrode forming conductive film on the surface of the first gate insulating film, and then patterning the gate electrode forming conductive film on the second conduction type TFT side while leaving the gate electrode forming conductive film on the first conduction type TFT side to form a gate electrode of the second conduction type TFT, the high-concentration second conduction type impurity introducing step of introducing high-concentration second conduction type impurities into the semiconductor film using the gate electrode forming conductive film and the second conduction type TFT gate electrode as a mask, the second gate electrode forming step of forming
Hayashi Masami
Ishiguro Hideto
Matsuo Minoru
Murai Hiroyuki
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Seiko Epson Corporation
Tsai Jey
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