Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-10-09
2004-06-01
Cac, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S620000, C438S622000
Reexamination Certificate
active
06743708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and more particularly to a technique for promoting miniaturization of a semiconductor device.
2. Description of the Background Art
A conventional DRAM has a storage node (SN) contact formed between bit lines (BL). As shown in
FIG. 14
, a conventional hole
40
P for the storage node contact is formed between bit lines
12
P as a minute cylindrical hole, for example. This minute hole
40
P is provided over a plug
11
P for the storage node contact. (Thus, the hole
40
P is formed in part of a region defined between the bit lines
12
P.)
Now, in reference to
FIGS. 15
to
18
, a method of forming the hole
40
P for the storage node contact using a conventional self-alignment contact (SAC) method will be described.
As shown in
FIG. 15
, the bit lines
12
P are patterned on an interlayer insulation film
31
b
P using a silicon nitride film
32
P serving as a hard mask (HM). A silicon nitride film
33
P serving as an etching stopper film is formed on the interlayer insulation film
31
b
P in such a manner as to cover the hard mask
32
P and the bit lines
12
P. Thereafter, an interlayer insulation film
34
P is formed.
Next, a resist
4
P is formed on the interlayer insulation film
34
P as shown in FIG.
16
. The interlayer insulation film
34
P is etched using the resist
4
P as a mask and the silicon nitride film
33
P as an etching stopper as shown in
FIG. 17
, following which the silicon nitride film
33
P on the interlayer insulation film
31
b
P is etched. Further, as shown in
FIG. 18
, the interlayer insulation film
31
b
P is etched until the plug
11
P is exposed.
With advancement in device miniaturization, requirements for the alignment margin between a bit line and a storage node contact, miniaturization of the bit line and the storage node contact, and their dimensional accuracy are becoming stricter. Indeed, the bit lines
12
P having a wiring width of not more than 70 nm and the hole
40
P for the storage node contact having a hole diameter of not more than 100 nm are becoming difficult to be formed in a stable shape.
Even by using the conventional SAC method, the silicon nitride films
33
P and
32
P which cover the bit lines
12
P may be etched as shown in
FIGS. 17 and 18
by causing etching to proceed further until the plug
11
P is exposed. In this case, the silicon nitride film
33
P may be etched so much that the bit lines
12
P are exposed into the hole
40
P, which problematically develops a short circuit between the bit lines
12
P and a plug (not shown) to be formed in the hole
40
P.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of etching an insulation film with better controllability than in the above described conventional minute hole.
Another object of the present invention is to provide the method of manufacturing a semiconductor device capable of insulating a conductive portion such as a bit line from another conductive portion with reliability.
Still another object of the invention is to provide a semiconductor device manufactured by the method capable of achieving the above-described two objects.
According to a first aspect of the present invention, the method of manufacturing a semiconductor device includes the following steps (a) to (e). The step (a) is to form a first insulation film on an underlying substrate and to provide a first conductive portion in the first insulation film. The step (b) is to form a conductive film on the first insulation film. The step (c) is to form a second insulation film on the conductive film leaving a space over the first conductive portion. The step (d) is to pattern the conductive film using the second insulation film as a mask to form a second conductive portion. The step (e) is to etch the first insulation film using the second insulation film as a mask after the step (d) to form a groove in the first insulation film.
The first insulation film is etched using the second insulation film formed on the second conductive portion as a mask (thereby forming the groove). Thus, the groove extends through the spacing of plane patterns of the second conductive portion and the second insulation film. Therefore, the groove is formed not only larger than a conventional minute hole formed in part of a region in the above spacing of plane patterns but also in a self-aligned manner. This allows the groove to be formed with better controllability in shape than the conventional minute hole. Further, the use of the second insulation film (as a mask) in common for forming the second conductive portion and the groove allows reductions in manufacturing time and manufacturing costs. Still further, forming the groove which is larger than the conventional minute hole after the step (d) can reduce the extent that the shoulder of the second insulation film is etched as compared to the conventional self-alignment contact method in which the minute hole is formed after forming another insulation film.
According to a second aspect of the present invention, the semiconductor device includes an underlying substrate, a first insulation film, a first conductive portion, a second conductive portion, a second insulation film and a sidewall-shaped insulating portion. The first insulation film is provided on the underlying substrate and has a groove with an opening on the opposite side of the underlying substrate. The first conductive portion is provided in the first insulation film and projects into the groove. The second conductive portion is provided on the first insulation film. The second insulation film is provided on the second conductive portion with the same plane pattern as the second conductive portion. The second conductive portion and the second insulation film have side faces continuing smoothly to a side face of the groove of the first insulation film. The sidewall-shaped insulating portion is provided in contact with a bottom face of the groove and a side face of a projection of the first conductive portion.
When a conductive material is provided on the first conductive portion, the conductive material can cover the first conductive portion with good step coverage thanks to the sidewall-shaped insulating portion. This can ensure an electric contact between the first conductive portion and the conductive material.
According to a third aspect of the present invention, the semiconductor device includes an underlying substrate, a first insulation film, a first conductive portion, a second conductive portion, a second insulation film and a side covering insulating portion. The first insulation film is provided on the underlying substrate and has a groove with an opening on the opposite side of the underlying substrate. The first conductive portion is provided in the first insulation film and exposes into the groove. The second conductive portion is provided on the first insulation film. The second insulation film is provided on the second conductive portion with the same plane pattern as the second conductive portion. The second conductive portion and the second insulation film have side faces continuing smoothly to a side face of the groove of the first insulation film. The side covering insulating portion extends from at least part of the side face of the second insulation film to at least part of the side face of the groove over the side face of the second conductive portion.
The side face of the second conductive portion is fully covered with the side covering insulating portion, allowing the second conductive portion to be insulated from another conductive portion with more reliability.
REFERENCES:
patent: 6297145 (2001-10-01), Ito
patent: 6559045 (2003-05-01), Chung
Watanabe Shinya
Yasumura Shunji
Cac Phat X.
Doan Theresa T.
Oblon, Spivak, McClelland, Maier & Neustadt PC.
Renesas Technology Corp.
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