Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-02-13
2007-02-13
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257SE21597
Reexamination Certificate
active
11083311
ABSTRACT:
An adhesion layer for causing a plug for electrically connecting a lower wiring and an upper wiring opposite to each other with an interlayer insulating film interposed therebetween to adhere to the interlayer insulating film is formed within a through hole for forming the plug, based on a predetermined aspect ratio represented by a ratio of a depth dimension of the through hole to a diameter dimension of the through hole.
REFERENCES:
patent: 5308793 (1994-05-01), Taguchi et al.
patent: 5486492 (1996-01-01), Yamamoto et al.
patent: 5913141 (1999-06-01), Bothra
patent: 5930669 (1999-07-01), Uzoh
patent: 5981378 (1999-11-01), Bothra
patent: 6130154 (2000-10-01), Yokoyama et al.
patent: 6133142 (2000-10-01), Tran et al.
patent: 6232221 (2001-05-01), Tran et al.
patent: 6258649 (2001-07-01), Nakamura et al.
patent: 6274475 (2001-08-01), Shields
patent: 6329681 (2001-12-01), Nakamura et al.
patent: 6348402 (2002-02-01), Kawanoue et al.
patent: 6358835 (2002-03-01), Kanamura
patent: 6444575 (2002-09-01), Yu et al.
patent: 6448657 (2002-09-01), Dorleans
patent: 6509277 (2003-01-01), Saito et al.
patent: 6593230 (2003-07-01), Kuroda
patent: 6717202 (2004-04-01), Sugawara et al.
patent: 2003/0036260 (2003-02-01), Nakamura
patent: 2003/0148603 (2003-08-01), Gardner
patent: 10-284603 (1998-10-01), None
patent: 11-040516 (1999-02-01), None
patent: 2000-091425 (2000-03-01), None
Stanley Wolf and Richard N. Tauber, Silicon Processing For The VLSI Era, 2000, Lattice Press, Second Edition, pp. 475-483.
Isaac Stanetta
Lebentritt Michael
Oki Electric Industry Co. Ltd.
Volentine Francos & Whitt PLLC
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