Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-01-29
1999-06-29
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438622, H01L 213205
Patent
active
059181460
ABSTRACT:
In the method of the present invention, for manufacturing a semiconductor device having a multilayered wiring structure, with an improved version of step of forming an interlayer insulation film, an aromatic or heterocyclic compound containing an Si--H group, and H.sub.2 O.sub.2 are introduced in a reaction chamber in which a semiconductor device is contained, and they are made to react with each other in a vacuum atmosphere of 665 Pa or lower at a temperature in a range of -10.degree. C. to +10.degree. C. Thus, an intermediate reaction product having an excellent planarization property in which a reflow thereof is promoted due to the Si--H group, is formed on the semiconductor substrate. The intermediate reaction product is then subjected to a heat treatment so as to induce a dehydration reaction, thereby obtaining a silicon-based oxide film having a reflow shape, a network structure and a low dielectric constant.
REFERENCES:
patent: 4781942 (1988-11-01), Leyden et al.
patent: 4992306 (1991-02-01), Hochberg et al.
S.K. Ghandi, VLSI Fabrication Principles: Silicon and Gallium Arsenide (2nd edition), John Wiley, pp. 724-725 (no month given), 1994.
Dobson et al., "Advanced SiO.sub.2 Planarization Using Silane and H.sub.2 O.sub.2 ", Semiconductor International, pp. 85-88, 1995.
Matsuura et al., "Novel Self-planarizing CVD Oxide for Interlayer Dielectric Applications", IEEE, pp. 117-120, 1994.
Nikkei Microdevices, pp. 105-112, 1995.
Matsuura et al., "Novel Self-planarizing CVD Oxide for Interlayer Dielectric Applications," International Electron Devices Meeting 1994, San Francisco, CA, Dec. 11-14, 1994, pp. 117-120.
Bowers Charles
Christianson Keith
Kabushiki Kaisha Toshiba
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