Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-03-28
2004-09-07
Rocchegiani, Renzo (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S768000, C438S786000, C438S902000
Reexamination Certificate
active
06787462
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-092535, filed Mar. 28, 2001; and No. 2001-303411, filed Sep. 28, 2001, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having buried metal wirings or interconnections, and more particularly, to a method of manufacturing a semiconductor device having buried metal wirings or interconnections with clean surfaces.
2. Description of the Related Art
Conventionally, aluminum has been widely used for forming wirings of an LSI device. However, in recent years, copper has come to be used in place of aluminum in order to improve the RC delay of the wirings and enhance the resistance of the wirings to the electromigration (EM).
Since many copper compounds have a low vapor pressure, it is difficult to process copper by means of RIE (reactive ion etching). Therefore, the copper wiring is formed mainly by the damascene process.
In general, in the damascene process, wiring grooves are formed in a surface region of an insulating layer (interlayer dielectric) provided on a semi-conductor substrate, followed by forming a metal layer on the entire surface of the interlayer dielectric so as to fill the wiring grooves with the metal. Then, the unnecessary metal layer portion present over the interlayer dielectric outside the wiring grooves is removed by a chemical mechanical polishing (CMP) so as to form damascene wirings. Particularly, a process is called a dual damascene process (DD process), in which a via hole is also formed in the step of forming the wiring grooves in the interlayer dielectric, and the metal layer is formed in a manner to fill the wiring grooves and also fill the via hole so as to form damascene wirings within the wiring grooves and, at the same time, to form a via plug in the via hole. In general, a diffusion preventing layer (barrier layer) such as a TiN layer is formed on the inner walls of the wiring grooves (and the via hole, if formed) before formation of the metal layer, particularly, a copper layer, in order to prevent copper from diffusing into the interlayer dielectric. Also, in order to prevent the diffusion of the damascene wiring metal and the via plug metal, a second insulating layer (cap insulating layer) such as a silicon nitride layer is formed on the interlayer dielectric to cover the formed damascene wirings.
It should be noted that the damascene wiring metal, particularly copper tends to be readily oxidized, is thus oxidized by, for example, the oxygen present in the ambient atmosphere, with the result that an oxide film is formed on the surface of the damascene wiring layers. The oxide film thus formed increases the resistance of the damascene wirings, with the result that the damascene wirings fail to exhibit the merit of the low resistivity inherent in copper. Such being the situation, a reducing treatment is applied to the damascene wiring layer, before formation of the second insulating layer noted above, so as to remove the oxide film formed on the surface of the damascene wiring layers.
As a result of an extensive research, the present inventors have found that, in the conventional process, the metal atoms, particularly copper atoms, in the damascene wiring layers are migrated during the reducing treatment so as to bring about an abnormal migration of the metal. Because of the abnormal migration of the metal, the damascene wiring metal layers are caused to extend over the interlayer dielectric. If the adjacent damascene wirings are electrically connected to each other via the abnormally migrated metal, a leak current flows between the adjacent damascene wirings. If it is possible to secure a sufficient distance between the adjacent damascene wirings, the abnormally migrated metal does not bring about the problem pointed out above. However, the wirings are being made finer and finer in recent years, and the distance between the adjacent damascene wirings is being made smaller and smaller. It follows that the generation of the leak current noted above is practically unavoidable.
The present inventors have also found as a result of an extensive research that, in the conventional process, the oxide film formed on the damascene wiring layer is not removed sufficiently by the reducing treatment. If a second insulating layer such as a silicon nitride film is formed on the damascene wiring layer under the state that the oxide on the damascene wiring layer is not removed sufficiently, it is much difficult to obtain desired device characteristics. In addition, the yield of semiconductor devices is caused to be lowered.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising:
(a) providing a semiconductor substrate including a first insulating layer having a buried copper wiring formed in its surface region;
(b) monitoring a total partial pressure of oxygen and water vapor within a process chamber in which the semiconductor substrate is to be introduced;
(c) in case where the total partial pressure of oxygen and water vapor within the process chamber exceeds a prescribed value as a result of the monitoring, carrying out a treatment to lower the total partial pressure of oxygen and water vapor to a level not higher than the prescribed value;
(d) introducing the substrate into the process chamber in which the total partial pressure of oxygen and water vapor is not higher than the prescribed value;
(e) subjecting the copper wiring to a reducing treatment within the process chamber; and
(f) forming a second insulating layer to cover the copper wiring which has been subjected to the reducing treatment.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate comprising a buried metal wiring;
estimating a state of oxidation on a surface of the metal wiring, followed by determining the conditions of a reducing treatment applied to the surface of the metal wiring based on the estimated state of oxidation and subsequently applying a reducing treatment to the surface of the metal wiring under the so determined conditions for the reducing treatment; and
forming an insulating layer to cover the reduced metal wiring.
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T. Takewaki et al., “A Novel Self-Aligned Surface-Silicide Passivation Technology for Reliability Enhancement in Copper Internconnects”, Symposium on VLSI Technology Digest of Technical Papers, pp. 31-32, (1995).
H. Yamaguchi et al., “A 7 Level Metallization With Cu Damascene Process Using Newly Developed Abrasive Free Polishing”, IEEE, pp. 264-266, (200).
Hiroshi Ikegami et al., U.S. Pending application Ser. No. 09/946,601, filed Sep. 6, 2001.
Iijima Tadashi
Watanabe Tadayoshi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Rocchegiani Renzo
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