Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-04-12
1998-11-10
Quach, T. N.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438620, 438629, 438641, 438648, 438677, 438655, H01L 21283
Patent
active
058343679
ABSTRACT:
In a method of manufacturing a semiconductor device having a multilayer wiring structure, it has at least two underlying layers having different etching conditions. Firstly, the native oxide film formed on one of the underlying layers, or a barrier metal layer, is etched out under etching conditions suitable for the barrier metal layer. Then, the surface of the barrier metal layer is capped with a plugging material having etching conditions similar to or substantially the same as those of the other one of the underlying layers, or a lower wiring layer. Subsequently, the native oxide film and the etching by-product formed on the lower wiring layer are etched out under etching conditions suitable for the lower wiring layer. Thereafter, contact holes for the two underlying layers are buried with a conductive substance to establish electric connection with their respective upper conductive layers. With the above described steps, the entire manufacturing process is significantly simplified and the time required for burying the contact holes is greatly reduced without remarkably increasing the contact resistance between the barrier metal layer and the lower wiring layer and the respective buried conductive substances.
REFERENCES:
patent: 5192713 (1993-03-01), Harada
patent: 5476814 (1995-12-01), Ohshima et al.
patent: 5563097 (1996-10-01), Lee
Otsuka Kenichi
Otsuka Mari
Kabushiki Kaisha Toshiba
Quach T. N.
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