Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-12-16
2001-08-21
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S270000, C438S272000, C438S294000, C438S296000
Reexamination Certificate
active
06277707
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates generally to the field of semiconductor device fabrication and more specifically to the fabrication of a semiconductor device having a recessed gate.
2. Background of the Invention
As integrated circuit technology advances and integrated circuit device dimensions decreases, it has become increasingly common to employ trench isolation methods to form trench isolation regions between active regions of a semiconductor device. Such trench isolation methods may employ chemical mechanical polishing (CMP) to provide a nominally planarized surface for an isolation trench that has been filled with an insulator. Typically, a CMP planarization of a wafer involves holding the wafer against a rotating polishing pad that is subjected to a silica-based alkaline slurry. The polishing pad also applies pressure against the wafer.
While it is desirable to use CMP planarization during the fabrication of semiconductor devices, the CMP planarization step may present some problems and drawbacks. For example, each additional CMP step leads to additional costs and additional processing time in the semiconductor fabrication process.
Additionally, a CMP step on a newly formed layer on the wafer may cause alignment targets thereon to lose their steps after the CMP method is performed. The CMP planarization step may also lead to “over polishing” (i.e., removal of material that was not intended to be removed). All of the above results may contribute to defective devices, loss of device yield, and lack of device reliability.
In prior art semiconductor devices having the elevated source/drain configuration, a CMP step is typically required to planarize the isolation regions. Furthermore, an additional CMP step (i.e., a pre-contact CMP step) is required to planarize the surfaces of the gates in these prior art devices before forming the contacts on the gate and source/drain region surfaces. This additional CMP step can lead to the problems mentioned above.
Thus, there is a need for a semiconductor device that can be fabricated with a reduction in the number of CMP planarization steps. What is further needed is a method of fabricating a semiconductor device with a reduction in the number of CMP planarization steps in the fabrication process.
SUMMARY OF THE INVENTION
The present invention advantageously provides a method of manufacturing a semiconductor device wherein the method eliminates the pre-contact chemical mechanical polishing (CMP) step that is required in the prior art.
The present invention provides an additional advantage of being able to planarize both the surfaces of isolation regions and the surfaces of gate regions in a single CMP step.
By reducing the number of CMP steps, the present invention further permits a reduction in cost and in processing time. The invention can also avoid or reduce CMP step problems that lead to defective devices, loss of device yield, and lack of device reliability.
The invention also advantageously provides a gate surface that is substantially at the same level as the surfaces of the source/drain regions, thereby facilitating the formation of electrical connections during the contact etching and formation process.
The invention also advantageously provides a structure that permits the source/drain regions to be doped at a sufficient level so as to reduce the fusion impurities that degrade the transistor characteristics.
The present invention provides the above advantages, as well as others, through a method of forming a semiconductor device on a substrate. The method comprises the steps of: forming a first recess in the substrate; depositing an insulator in the first recess so that an isolation region is formed when the first recess is filled with the insulator; forming a second recess in a predetermined area of the substrate; forming a recess insulation layer on the surface of the second recess; depositing a conductive material on the recess insulation layer and in the second recess so that a gate region is formed when the second recess is filled with the conductive material; removing a sufficient amount of the insulator and the conductive material so that the top surfaces of the insulator, the conductive material and the substrate are substantially at the same level.
REFERENCES:
patent: 4663832 (1987-05-01), Jambotkar
patent: 4818725 (1989-04-01), Lichtel, Jr. et al.
patent: 5175122 (1992-12-01), Wang et al.
patent: 5422289 (1995-06-01), Pierce
patent: 5459096 (1995-10-01), Venkatesan et al.
patent: 5492858 (1996-02-01), Bose et al.
patent: 5494857 (1996-02-01), Cooperman et al.
patent: 5627094 (1997-05-01), Chan et al.
patent: 5702977 (1997-12-01), Jang et al.
patent: 5733810 (1998-03-01), Baba et al.
patent: 5763310 (1998-06-01), Gardner
Lee Brian R.
Miller Gayle W.
Taravade Kunal N.
LSI Logic Corporation
Malsawma Lex H.
Smith Matthew
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