Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-02-18
2002-07-09
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S263000, C438S950000
Reexamination Certificate
active
06417086
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a nonvolatile memory and a logic circuit and, more particularly, an integrated circuit device having a double-layers gate structure and a single-layer gate structure and a method of manufacturing the same.
2. Description of the Related Art
In recent years, an integrated circuit semiconductor device has been utilized in various fields including various information devices such as a mobile device, an IC card, etc. In such semiconductor device, a nonvolatile memory such as EEPROM (Electrically Erasable Programmable ROM), etc., from/into which the user can electrically erase/program data, and a CMOS logic circuit such as ASIC (Application Specific Integrated Circuit), etc. are integrated on the same chip.
FIG. 12
is a sectional view showing a structure of a semiconductor device having the EEPROM and the CMOS logic circuit in the prior art. As shown in
FIG. 12
, a high voltage operating circuit (HV circuit), which is operated by a high voltage such as about 20 V necessary for erasing/programming of a memory cell, is installed in the neighborhood of the EEPROM.
As shown in
FIG. 12
, each memory cell of the EEPROM is composed of a memory transistor and a selector transistor connected in series with this memory transistor. The memory transistor is constructed as a double-layers gate which consists of an underlying gate oxide film
116
having a thin tunnel oxide film
118
in its partial area, a floating gate
120
b
, an interlayer gate oxide film
122
, and a control gate
126
b.
When the voltage is applied to the control gate
126
b
, the tunnel current is generated via the tunnel oxide film
118
to inject/extract electrons into/from the floating gate
120
b
. Binary digits “1”, “0” are decided based on whether or not the storage charge exists in the floating gate
120
b
. Since the memory transistor is isolated from the periphery, the memory transistor can still hold the storage charge after the power supply is turned off if the charge is accumulated in the memory transistor once.
Basically the selector transistor, the transistor in the HV circuit, and the CMOS transistor in the logic circuit other than the memory transistor are formed as a single-layer gate. In many cases, in order to achieve the process matching, these transistors are formed as the double-layers gate structure to mate with the structure of the memory transistor, and a structure in which overlying and underlying gate electrodes are short-circuited partially is used.
In the double-layers gate structure, a thickness of the layer to be etched by the dry etching becomes considerably large in forming gate patterns rather than the case where the single-layer gate structure is formed. Since a time required for the etching is increased longer as the to-be-etched layer becomes thicker, the used etching mask is requested to achieve the high etching resistance. In addition, since a surface of the etching mask is also etched at the time of etching, the predetermined thickness or more is needed for the etching mask.
For example, if a resist mask is used as the etching mask, a necessary mask thickness becomes considerably large because the resist is ready to be etched. Also, since the resist is gasified during the etching process to generate new reaction adhesive, drip or deformation of the mask pattern is caused. Therefore, in forming the double-layers gate pattern, normally an inorganic film such as an SiNx film is utilized in place of the resist mask. The inorganic film mask is normally called a hard mask.
However, since a thickness of the to-be-etched layer is still considerably thick in the double-layers gate structure even if the hard mask is used, it is essentially difficult to form the fine pattern. Therefore, like the LSI for the IC card including the nonvolatile memory, if the CMOS logic circuit which is integrated together with the EEPROM on the same chip are requested to be formed as the fine patterns, as shown in
FIG. 12
, the double-layers gate structure is formed in the EEPROM area regardless of the burden of the process, nevertheless the single-layer gate structure is formed in the CMOS logic circuit area.
As a result, a structure which consists of the logic circuit with the single-layer gate structure and the memory cell and its peripheral circuit with the double-layers gate structure is formed on the same chip.
A method of manufacturing a LSI including the EEPROM and including the single-layer gate structure and the double-layers gate structure in the prior art will be explained with reference to
FIG. 13A
to
FIG. 14H
hereunder.
First, as shown in
FIG. 13A
, an n well
112
is formed in a part of the CMOS logic circuit area on a p-type semiconductor substrate
110
. Then, respective circuit areas are defined by a field oxide film
114
in the LOCOS step so as to electrically isolate respective circuit areas.
Then, an n-type shallow impurity diffusion area is formed under a tunnel oxide film area of the EEPROM cell. Also, a silicon oxide film (SiO2)
116
of about 350 Å thickness is formed as a gate oxide film on a surface of the substrate. The gate oxide film
116
is removed from a tunnel oxide film forming area by the etching, and then a tunnel oxide film
118
made of a thin SiO2 film of about 90 Å thickness is formed in this area.
Then, as shown in
FIG. 13B
, a first polysilicon film
120
is formed. Phosphorus (P) is doped into this film to reduce the resistance value, as occasion demands. Then, a so-called ONO (oxide
itride/oxide) film
122
serving as an interlayer gate insulating film is formed. This ONO film
122
is formed of three layers which consists of a SiO2 film obtained by thermally oxidizing a surface of the first polysilicon film
120
, a SiNx film formed by the CVD method, and an SiO2 film obtained by oxidizing a surface of the SiNx film.
Then, as shown in
FIG. 13C
, the ONO film
122
, the first polysilicon film
120
, and the gate oxide film
116
formed thereunder are removed by the etching from the CMOS logic circuit area in which the single-layer gate structure is to be formed.
Then, as shown in
FIG. 13D
, in the CMOS logic circuit area, a thin gate oxide film
124
is formed to mate with a size of a fine transistor to be formed in this area. After this, a second polysilicon film
126
is formed on an overall surface of the substrate. Ions are implanted into a channel area in the logic circuit area to control a threshold value of the transistor, as occasion demands, and thus the impurity concentration is adjusted previously.
Then, as shown in
FIG. 14E
, an SiNx film
128
used as a hard mask is formed on an overall surface of the substrate. Since this SiNx film
128
is used as an etching mask in forming the double-layers gate pattern in the EEPROM area, normally such SiNx film
128
must be formed to have a large thickness of 2000 Å or more.
Then, as shown in
FIG. 14F
, mask patterns
128
a
to
128
e
for respective gates are formed by selectively etching the SiNx film
128
. Then, the second polysilicon film
126
is etched by the RIE (Reactive Ion Etching) method using the mask patterns as the etching mask. In the EEPROM area, a surface of the interlayer gate insulating film
122
is exposed because the second polysilicon film
126
is etched. In the CMOS logic circuit area, single-layer gates
151
,
152
are formed.
In this manner, the single-layer gates which are formed in the CMOS logic circuit area are patterned simultaneously by using the thick hard mask which is used to form the double-layers gates.
Then, as shown in
FIG. 14G
, the CMOS logic circuit area is covered with a resist film
134
. In the EEPROM area and the HV circuit area, the etching of the interlayer gate insulating film
122
and the first polysilicon film
120
is continued while using the mask patterns
128
a
to
128
c
. Thus, the double-layers gates
153
,
154
,
155
are obtained. Then, the resist film
134
for covering the CMOS logic circuit area is re
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Weiss Howard
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