Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2002-04-10
2004-12-21
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S514000, C438S149000
Reexamination Certificate
active
06833313
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device using ion implantation, and more specifically, to an ion implantation method using a resist mask and a method of removing the resist mask. Note that the ion implantation in the present invention indicates ion beam irradiation and includes both ion beam irradiation with mass separation and ion beam irradiation without mass separation.
2. Description of the Related Art
In steps of manufacturing a semiconductor element, introduction (doping) of an impurity element to semiconductor by ion implantation is performed for valence electron control. An ion implantation method is roughly described as a method of dissociating a gas including an element belonging to group 13 or group 15 of the periodic table, such as diborane (B
2
H
6
) or phosphine (PH
3
), to ionize it and accelerating the ion by an electric field to physically implant it into a substrate on which a semiconductor element is formed. With respect to ionic species produced at this time, it is known that plural species are produced when they are classified by mass number. A method of mass-separating these ions and implanting a single ion is generally called the ion implantation method. Also, a method of implanting an ion without particularly performing mass separation is called an ion dope method, a plasma dope method, or the like.
In all cases, it is necessary to selectively implant an ion into a predetermined region of a semiconductor to form an impurity region. Thus, a method of forming a resist pattern in advance to use it as a mask is used. Hereinafter, ion implantation using a resist as a mask and removal of the resist used as the mask will be described.
FIG. 4
shows a step of forming source and drain regions of TFTs of a CMOS structure. Since it is necessary to selectively introduce phosphorus (P) into source and drain regions
105
of an n-channel TFT
111
, a p-channel TFT
110
is masked by a resist
107
. When ion implantation is performed with this state, an ion including P is implanted into the source and drain regions
105
of the n-channel TFT
111
through a gate insulating film
102
using a gate electrode
101
as a mask.
Subsequently, the process advances to a step of removing the resist 107 as the mask. A method of removing the resist using a special stripper or a method of ashing (etching) the resist by supplying an oxygen radical is generally used. An ashing step is performed using high frequency (RF) plasma with parallel flat plates, high density plasma process with inductive coupled plasma (ICP), microwave excitation plasma, or the like.
However, there is a problem that the resist cannot be easily removed in the step of removing the resist. In ion implantation, since an ion is accelerated by a high electric field to implant it into a substrate, when ion collision is caused, the kinetic energy is converted into heat energy to heat the substrate and objects formed thereon. Although the heated temperature depends on an ion implantation condition, it is known that the temperature can rise up to about 200° C.
In contrast to this, only baking process at about 100° C. to 140° C. is performed for the resist formed as the mask. Thus, when the resist is substantially heated at a temperature higher than that temperature, a chemical change such that the surface thereof is altered and cured is produced. Generally, the thus altered resist cannot be removed even by using the special stripper. Thus, ashing having a stronger removal effect is generally used.
Further, when a P ion is implanted, P reacts with a novolac resin as a resist material so that an altered layer in which a structure is changed is produced. Since the altered layer is chemically stable, it cannot be easily removed by a conventional stripper or a conventional ashing method. When a dose of P is large, such a tendency becomes remarkable. Thus, ashing process for a very long time is required. Also, since the resist cannot be completely removed by only ashing process, there is a case where a residue thereof is produced, causing inconvenience in later steps.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above, and an object of the present invention is to provide a method of manufacturing a semiconductor device, in which removal of the resist after ion implantation becomes easy.
In order to attain the above-mentioned object, the present invention is characterized by comprising the steps of simultaneously implanting an ion of an impurity element having a conductivity type and an ion of a rare gas element and then removing a resist mask.
Further, the present invention is characterized by comprising: a first step of implanting an ion of an impurity element having a conductivity type; a second step of implanting an ion of a rare gas element; and a third step of removing a resist mask after the first step and the second step.
Further, the present invention is characterized by comprising: a first step of implanting an ion of an impurity element having a conductivity type; a second step of implanting an ion of a rare gas element; and a third step of removing a resist mask after the first step and the second step have been performed in succession.
Further, the present invention is characterized by comprising the steps of implanting an ion of a rare gas element and then removing a resist mask.
Also, a method of separately performing a first step of implanting an ion of an impurity element having a conductivity type before a resist mask is removed and a second step of implanting an ion of a rare gas element in two stages can be applied. In this case, the second stage (second step) is performed at a lower accelerating voltage than that in the first stage (first step).
Also, a method of performing a step of implanting an ion of an impurity element for imparting a conductivity type and a step of implanting an ion of a rare gas element in succession before a resist mask is removed can be applied.
The rare gas element may be at least one selected from the group consisting of helium, krypton, argon, and xenon.
Also, as the impurity element for imparting a conductivity type, there is P (phosphorus), As (arsenic), B (boron), or the like.
Also, the present invention is characterized by comprising a stage of implanting the ion of the rare gas element before ashing of the resist mask.
A typical example includes using P as the impurity element for imparting a conductivity type and performing Ar ion implantation following P ion implantation. Thus, an ashing rate of the resist can be improved. Also, even when an Ar ion and a P ion are simultaneously implanted, the same effect is obtained.
As described above, it is found that, when the physical action of the ion is applied to the altered layer in the surface of the resist, which is produced in the ion dope step, ashing of the resist mask in which the altered layer is formed can be easily performed due to a reason such that severing of a bond for which chemical decomposition is usually difficult becomes possible or the altered layer is chipped away by the impact of ion implantation. In all cases, in the ion implantation step of adding an impurity element having one conductivity type to a semiconductor, a resist pattern is used as a mask and an ion of an rare gas element is implanted simultaneous with an ion of the impurity element having one conductivity type or implanted after implantation of the ion of the impurity element having one conductivity type. Thus, ashing process of removing the resist pattern can be easily performed.
REFERENCES:
patent: 2002/0119585 (2002-08-01), Yamazaki et al.
patent: 2 230 335 (1998-06-01), None
patent: 10-135182 (1998-05-01), None
Elms Richard
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
Smith Brad
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