Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-04
2004-04-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S762000, C438S770000, C438S787000, C438S790000, C257S635000, C257S639000, C257S640000
Reexamination Certificate
active
06723641
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for manufacturing a semiconductor device, and more particularly to a technique to reduce defective film formation.
2. Description of the Background Art
FIGS. 68 and 69
are a plan view and a cross section, respectively, showing an exemplary structure of an AND-type flash memory.
FIG. 69
is the cross section taken along the position Q
1
—Q
1
of FIG.
68
.
For example, in a surface of a silicon substrate
1
, element formation regions are insulated from one another by a plurality of trench isolation oxide films
2
. On a surface of the element formation region, sources
3
a
and
18
a
serving as a source line and drains
3
b
and
18
b
serving as a bit line are formed, being spaced from one another. The sources
3
a
and
18
a
and the drains
3
b
and
18
b
are extended almost in parallel to one another in a longitudinal direction of
FIG. 68. A
plurality of control gates
8
serving as word lines are formed in a traverse direction of
FIG. 68
, being insulated from one another. The position Q
1
—Q
1
is determined along the control gates
8
.
On the sources
3
a
and
18
a
, the drains
3
b
and
18
b
and the trench isolation oxide films
2
, an oxide film made of TEOS (Tetra Ethyl Ortho Silicate: Si(C
2
H
5
O)
4
) (hereinafter referred to as “TEOS oxide film”) is formed as a thick insulating film
6
. A channel region
1
a
is located in a region of the silicon substrate
1
sandwiched between the sources
3
a
and
18
a
and the drains
3
b
and
18
b
. A floating gate
5
is formed over the channel region
1
a
with a tunnel oxide film
4
interposed therebetween. On the floating gate
5
, a phosphor-doped amorphous silicon film
9
, an ONO (Oxide-Nitride-Oxide) film
7
and a control gate
8
are layered in this order. The control gate
8
includes a polysilicon film
8
a
and a tungsten silicide film
8
b
formed thereon.
A silicon oxide film
11
is formed as an insulating film on the control gate
8
. Further on the silicon oxide film
11
, an interlayer insulating film
21
is formed. Memory cell transistors (Tr
1
, Tr
2
, . . . ) each include the sources
3
a
and
18
a
, the drains
3
b
and
18
b
, the floating gate
5
and the control gate
8
. In order to read information stored in the transistor Tr
2
, a predetermined voltage is applied to the sources
3
a
and
18
a
and a predetermined voltage is applied to the control gate
8
corresponding to the transistor Tr
2
. At this time, whether the transistor Tr
2
is turned on or not depends on the amount of electrons accumulated in the floating gate
5
of the transistor Tr
2
. When the transistor Tr
2
is turned on, currents flow between the sources
3
a
and
18
a
and the drains
3
b
and
18
b.
A plurality of memory cell transistors Tr
1
, Tr
2
, . . . share the sources
3
a
and
18
a
and the drains
3
b
and
18
b
, and are connected in parallel to one another to constitute an AND-type flash memory.
In a flash memory, there are capacitance between the floating gate
5
and the silicon substrate
1
(mainly consisting of the capacitance of the tunnel oxide film
4
: hereinafter referred to as “first gate capacitance”) and capacitance between the floating gate
5
and the control gate
8
(hereinafter referred to as “second gate capacitance”). Generally required is a flash memory which allows fast write and fast erase to/from memory cells. To satisfy this requirement, it is desirable that the second gate capacitance should be stably larger than the first gate capacitance.
Specifically, it is required that the film thickness of the ONO film
7
should be thin, allowing excellent repeatability and uniformity. For example, a target value of film thickness for each of a bottom silicon oxide film (closer to the silicon substrate
1
), a silicon nitride film and a top silicon oxide film (away from the silicon substrate
1
) constituted of the ONO film
7
is about 5 nm, aiming for a very thin thickness. Very strict film characteristics are required, that variation of film thickness obtained in one process (one batch) should be within the target value ±5% or lower with excellent repeatability.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a technique for film formation with film thickness easily controlled in the chemical vapor deposition method, for example, a technique applicable to a case where a silicon oxide film such as the bottom silicon oxide film of the ONO film
7
is formed on a semiconductor substrate on which a TEOS oxide film such as the thick insulating film
6
exists. As obviously can be seen from the following preferred embodiments, however, the present invention is intended not only for use in film formation of an oxide film but also for use in other film formation, for example, of a nitride film with its film thickness easily controlled.
The present invention is directed to a method of manufacturing a semiconductor device. According to a first aspect of the present invention, the method of manufacturing a semiconductor device includes steps (a) to (c). In the step (a), a first layer is formed by performing the chemical vapor deposition method on a semiconductor substrate at a first temperature and a first pressure for a first period. In the step (b), a heat treatment is performed under an inert gas atmosphere while exhausting a gas from the vicinity of the semiconductor substrate. In the step (c), a second layer is formed by performing the chemical vapor deposition method at a second temperature and a second pressure for a second period. The second temperature is higher than the first temperature and the second pressure is lower than the first pressure. The heat treatment is performed in the step (b) at a third temperature and a third pressure. The third temperature is equal to or higher than the second temperature and the third pressure is equal to or lower than the second pressure.
The gas used for forming the first layer in the step (a) is desorbed from the first layer in the step (b). Therefore, it is possible to reduce an ill effect of the gas in the film formation of the second layer of the step (c).
According to a second aspect of the present invention, the method of manufacturing a semiconductor device includes steps (a) to (c). In the step (a), a first layer is formed on both a main surface and a back surface of the semiconductor substrate by performing the chemical vapor deposition method on the semiconductor substrate at a first temperature and a first pressure. In the step (b), the first layer formed on the back surface is removed. In the step (c), a second layer is formed by performing the chemical vapor deposition method at a second temperature and a second pressure for a second period. The second temperature is higher than the first temperature and the second pressure is lower than the first pressure.
The ill effect of the gas contained in the first layer, which is used for forming the first layer, on the film formation of the second layer in the step (c) becomes smaller.
According to a third aspect of the present invention, the method of manufacturing a semiconductor device includes steps (a) to (c). In the step (a), a first layer is formed on both a main surface and a back surface of a semiconductor substrate by performing the chemical vapor deposition method on the semiconductor substrate at a first temperature and a first pressure. In the step (b), the first layer formed on the back surface is covered. In the step (c), a second layer is formed by performing the chemical vapor deposition method at a second temperature and a second pressure. The second temperature is higher than the first temperature and the second pressure is lower than the first pressure. The first layer is covered in the step (b) with a film which prevents gas desorption from the first layer in the step (c).
The ill effect of the gas contained in the first layer, which is used for forming the first layer, on the film formation of the second layer in the step (c) becomes
Berry Renee R.
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
LandOfFree
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3260334