Method of manufacturing semiconductor device and...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S637000, C438S687000, C257S759000, C257S760000, C257S762000, C257SE23145

Reexamination Certificate

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06962870

ABSTRACT:
A method of manufacturing a semiconductor device comprising forming a protective film on a surface of a lower-layer interconnection, and forming a multilayer-structured film by stacking a first porous film, a first non-porous film, a second porous film, and a second non-porous film on a surface of the protective film in this order, and forming a via hole and an interconnect trench. After a resist mask is removed, protective film exposed at a bottom of the via hole is removed. An upper-layer interconnection of dual damascene structure is formed by embedding an interconnect material in the via hole and the interconnect trench.The first non-porous film includes a first layer has a high etching selectivity ratio relative to the protective film, and a second layer has a high etching selectivity ratio relative to the resist mask and the second porous film.

REFERENCES:
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patent: 6515365 (2003-02-01), Higashi et al.
patent: 6525428 (2003-02-01), Ngo et al.
patent: 6737744 (2004-05-01), Fukuyama
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patent: 2004/0094839 (2004-05-01), Fitzsimmons et al.
patent: 2003-100866 (2003-04-01), None
Hasegawa et al.; “Copper Dual Damascene Interconnects with Low-K (KEFF21 3.0) Dielectrics Using Flare™ and an Organo-Silicate Hard Mask”; International Electron Devices Meeting (IEDM), pp. 623-626, (1999).

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