Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-01-04
2005-01-04
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S618000, C438S778000, C438S780000, C438S620000, C438S622000, C438S637000, C438S638000, C438S643000, C438S645000, C438S674000
Reexamination Certificate
active
06838370
ABSTRACT:
The present invention is directed to suppressing the rise of a dielectric constant of insulating film during a procedure of burying wiring in semiconductor devices by using a damascene process, and it is also directed to simplifying a process of manufacturing the semiconductor devices. In terms of a process step of forming protection film on a metal layer during the damascene process, there is employed a combined arrangement of a wash unit where particles are removed from polished substrates with a processing unit where a solution containing an organic substance such as benzotriazole, which tends to be bound to the metal layers, is applied to the metal layers over the substrates after the particles are removed therefrom. For the combined arrangement of the processing unit and the wash unit, either a batch processing unit or a mono/serial processing unit can be employed.
REFERENCES:
patent: 5736770 (1998-04-01), Asai et al.
patent: 5795828 (1998-08-01), Endo et al.
patent: 6150257 (2000-11-01), Yin et al.
patent: 6150270 (2000-11-01), Matsuda et al.
patent: 6153521 (2000-11-01), Cheung et al.
patent: 6323131 (2001-11-01), Obeng et al.
patent: 6350687 (2002-02-01), Avanzino et al.
patent: 5-315331 (1993-11-01), None
patent: 8-64594 (1996-03-01), None
patent: 10-163208 (1998-06-01), None
patent: 11-154653 (1998-06-01), None
patent: 10-229084 (1998-08-01), None
Goto Hideto
Niuya Takayuki
Ono Michihiro
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Fourson George
Maldonado Julio J.
Tokyo Electron Limited
LandOfFree
Method of manufacturing semiconductor device and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing semiconductor device and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor device and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3396282