Method of manufacturing semiconductor device

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

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438585, H01L 213205, H01L 214763

Patent

active

061658782

ABSTRACT:
A method of manufacturing a semiconductor device which prevents a short circuit between a gate electrode and a diffusion layer region if a contact hole is shifted from its proper position. A material having an etch selectivity to an interlayer insulation film is formed over the gate electrode to serve as a cover against the formation of a contact hole. A material is not formed over an interconnect line which is required to be exposed to a contact hole.

REFERENCES:
patent: 5059548 (1991-10-01), Kim
patent: 5174858 (1992-12-01), Yamamoto et al.
patent: 5668052 (1997-09-01), Matsumoto et al.
S. Wolf and R.N. Tauber, Silicon Processing for the VLSI Era--Process Technology, (Lattice Press, California, 1986), vol. 1, pp. 418-420.
S. Wolf, Silicon Processing for the VLSI Era--Process Integration, (Lattice Press, California, 1990), vol. 2, pp. 238-239.

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