Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2008-01-28
2010-02-02
Ghyka, Alexander G (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S584000, C438S634000, C438S689000, C257SE21680, C257SE21667
Reexamination Certificate
active
07655569
ABSTRACT:
The invention prevents a wiring layer in a memory region from being exposed to prevent a change in wire resistance and degradation of reliability. A SiO2film as an etching stopper film which transmits ultraviolet light is formed on pad electrodes and an interlayer insulation film. Then, the SiO2film on the pad electrodes is etched selectively and the SiO2film in an EPROM region is left. A silicon nitride film and a polyimide film are then formed on the SiO2film and on the pad electrodes where the SiO2film is removed, as a protection film which does not transmit ultraviolet light. The silicon nitride film and the polyimide film on the pad electrodes and in the EPROM region are then selectively removed by etching. Since the SiO2film functions as an etching stopper at this time, the interlayer insulation film under the SiO2film is prevented from being etched and a control gate line metal layer is prevented from being exposed.
REFERENCES:
patent: 4853761 (1989-08-01), Ikeda
patent: 2003/0080428 (2003-05-01), Izumitani et al.
patent: 2004/0166696 (2004-08-01), Lee
patent: 2005/0161825 (2005-07-01), Watanabe
patent: 2005-243127 (2005-09-01), None
Inaba Yuichi
Morikawa Shigehiro
Yamada Yutaka
Ghyka Alexander G
Morrison & Foerster / LLP
Mustapha Abdulfattah
Sanyo Electric Co,. Ltd.
Sanyo Semiconductor Co. Ltd.
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