Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

2005-02-01

2005-02-01

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S258000, C438S266000, C438S595000

Reexamination Certificate

active

06849553

ABSTRACT:
The manufacturing method of the present invention forms a patterned gate layer140das a dummy circuit on a peripheral portion of a chip900simultaneously with formation of a patterned gate layer140ain a memory area1000, prior to formation of an insulating layer270over whole surface of a semiconductor substrate. This causes appearance of a new protrusion on the top surface of the insulating layer270in the peripheral portion of the chip900. The insulating layer270is subsequently polished by chemical mechanical polishing (CMP) technique. The presence of the new protrusion on the top surface of the insulating layer270effectively reduces the polishing rate and thereby decreases the polishing degree on the peripheral portion of the chip900. The technique of the present invention thus preferably prevents exposure of gate electrodes142on a part of the chip900close to a scribing area3000between adjoining chips900(that is, on the peripheral portion of the chip900) in the process of polishing the insulating layer270.

REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5663923 (1997-09-01), Baltar et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6396158 (2002-05-01), Travis et al.
patent: 6413821 (2002-07-01), Ebina et al.
patent: 6531350 (2003-03-01), Satoh et al.
patent: 6566196 (2003-05-01), Haselden et al.
patent: 6599801 (2003-07-01), Chang et al.
patent: 6656794 (2003-12-01), Shibata
patent: 6762092 (2004-07-01), Yuan et al.
patent: 20030003661 (2003-01-01), Lee
patent: 20030157767 (2003-08-01), Kasuya
patent: 20030166320 (2003-09-01), Kasuya
patent: 20030166321 (2003-09-01), Kasuya
patent: 20030166322 (2003-09-01), Kasuya
patent: 20030186505 (2003-10-01), Shibata
patent: 20030211691 (2003-11-01), Ueda
patent: A 7-161851 (1995-06-01), None
patent: 11-162981 (1999-06-01), None
patent: B1 2978477 (1999-09-01), None
patent: 11-289015 (1999-10-01), None
patent: 2001-148434 (2001-05-01), None
patent: A 2001-156188 (2001-06-01), None
patent: 2001-156275 (2001-06-01), None
U.S. patent application Ser. No. 10/636,562, Inoue, filed Aug. 8, 2003.
U.S. patent application Ser. No. 10/636,581, Yamamukai, filed Aug. 8, 2003.
U.S. patent application Ser. No. 10/636,582, Inoue, filed Aug. 8, 2003.
U.S. patent application Ser. No. 10/614,985, Inoue, filed Jul. 9, 2003.
U.S. patent application Ser. No. 10/689,993, Kasuya, filed Oct. 22, 2003.
U.S. patent application Ser. No. 10/689,990, Kasuya, filed Oct. 22, 2003.
U.S. patent application Ser. No. 10/689,987, Kasuya, filed Oct. 22, 2003.
U.S. patent application Ser. No. 10/690,025, Kasuya, filed Oct. 22, 2003.
U.S. patent application Ser. No. 10/052,549, Ebina et al., filed Jan. 23, 2002.
U.S. patent application Ser. No. 10/052,255, Ebina et al. filed Jan. 23, 2002.
U.S. patent application Ser. No. 09/953,856, Ebina et al., filed Sep. 18, 2001.
U.S. patent application Ser. No. 09/953,855, Ebina et al., filed Sep. 18, 2001.
U.S. patent application Ser. No. 10/234,095, Ebina et al., filed Sep. 5, 2002.
U.S. patent application Ser. No. 10/244,627, Ebina et al., filed Sep. 17, 2002.
U.S. patent application Ser. No. 10/234,197, Ebina et al., filed Sep. 5, 2002.
U.S. patent application Ser. No. 10/244,623, Ebina et al., filed Sep. 17, 2002.
Yutaka Hayashi et al.; “ Twin MONOS Cell with Dual Control Gates”; 2000, IEEE VLSI Technology Digest of Technical Papers; 2000.
Kuo-Tung Chang et al. “ A New Sonos Memory Using Source-Side Injection for Programming”;IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998 pp 253-255.
Wei-Ming Chen et al., A Novel Flash Memory Device with S Plit Gate Source Side Injection and ONO Charge Storage Stack (SPIN); VLSI Technology Digest of Technical Papers; 1997 pp 63-34.

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