Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-06
2003-10-14
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S643000, C438S648000, C438S681000, C438S685000
Reexamination Certificate
active
06632738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention at relates to methods of manufacturing semiconductor devices including the process of forming a multi-layer interconnection structure according to a damascene method. The invention more particularly relates to a method of manufacturing a semiconductor device having an improved electromigration resistance at the interface between a via and an interconnection and improved reliability for the multi-layer interconnection.
2. Description of the Related Art
A damascene method has been applied as a conventional method of forming a multi-layer interconnection in a semiconductor device.
FIGS. 1A
to
1
C are sectional views showing steps in a method of manufacturing a semiconductor device according to such a conventional damascene method in the order of manufacture. As shown in
FIG. 1A
, an interlayer insulating film
30
, for example, is formed on a diffusion layer
21
in a MOS transistor. A via
31
is formed in connection with the diffusion layer
21
in the interlayer insulating film
30
. An interlayer insulating film
32
is formed on the interlayer insulating film
30
and the via
31
. A first layer copper interconnection
22
is formed in connection with the via
31
in the interlayer insulating film
32
. A barrier layer
23
of a silicon nitride (SiN) film is then formed. An interlayer insulating film
24
and an oxide layer
25
are placed on the barrier layer
23
.
Then, as shown in
FIG. 1B
, a groove
27
for a second layer copper interconnection is formed in the oxide layer
25
by dry etching, and a via hole
26
is formed in the interlayer insulating film
24
and the barrier layer
23
. Then, a barrier metal layer (not shown) of TiN, TaN or the like is formed by sputtering. Seed layer of Cu (not shown) is formed by sputtering.
Then, as shown in
FIG. 1C
, the via hole
26
and the groove
27
are plated with Cu to form a via
28
and a second layer copper interconnection
29
simultaneously. Then, the surface is planarized by CMD (Chemical Mechanical Polishing). The double layer interconnection structure is thus formed. The above-described process is repeated to form a desired multi-layer interconnection structure including three or more interconnection layers.
Japanese Patent Laid-Open Publication No. Hei. 5-304148 discloses a method of forming a multi-layer interconnection by a damascene method. According to the method, impurity ions are implanted into a lower interconnection layer followed by thermal treatment in vacuum. According to the disclosure, the impurity can be deposited on the surface of the lower interconnection layer to form a stabilized layer, so that a natural oxide film can be suppressed from being formed on the surface layer of the lower interconnection layer. As a result, the electric resistance at the contact portion can be lowered. Note that the ions are of an element of the same group as the element forming the lower interconnection layer or 7-group element ions.
Japanese Patent Laid-Open Publication No. Hei. 8-203900 discloses another method of forming a multi-layer interconnection by a damascene method. According to the disclosed method, the surface layer of an upper interconnection layer is turned amorphous, and then the amorphous layer is removed. According to the method, the surface of the upper interconnection layer is planarized, and a stabilized shape results. As a result, the reliability of the semiconductor device improves.
Furthermore, Japanese Patent Laid-open Publication Nos. 2000-12686, Hei. 11-87499 and Hei. 11-288935 also disclose methods of manufacturing a semiconductor device by a damascene method.
These conventional methods of manufacturing a semiconductor device by the damascene method however suffer from the following disadvantage. In a multi-layer interconnection formed by the damascene method, there are defects such as a micro void and an interface state at the interface between each interconnection and the via. Even having such a defect, the interface may be electrically connected right after it is formed. However, as described in Kawasaki, Applied Physics Vol. 68, 1999, P. 1226, a long term, high density current flow across the interface causes the electron flow momentum to be converted into the momentum of Cu atoms, which causes the Cu atoms to drift in the defect portion as a diffusion passage. As a result, disconnection results at the interface portion. In other words, electromigration is caused. The reliability of the semiconductor device having the multi-layer interconnection degrades as a result.
There has been no effective solution suggested for the disadvantage. According to the method disclosed by Japanese Patent Laid-Open Publication No. Hei. 5-304148, for example, an impurity layer is formed at the surface layer of a lower layer interconnection. In this case, electromigration is caused at the interfaces between the impurity layer and the metal forming the lower layer interconnection, and between the impurity layer and the via. According to the method disclosed by Japanese Patent Laid-Open Publication No. Hei. 8-203900, only the upper layer interconnection is turned amorphous, and the amorphous portion is removed by CMP. This method therefore does not contribute to a reduction in the defects at the interface between the lower layer interconnection and the via.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of manufacturing a semiconductor device allowing defects caused at the interface between each interconnection and a via in a multi-layer interconnection to be reduced in forming the multi-layer interconnection in the semiconductor device, so that electromigration at the interface may be reduced, and the reliability of the semiconductor device may be improved.
By the method of manufacturing a semiconductor device according to the present invention, a multi-layer interconnection structure is formed by a damascene method. The method comprises the steps of forming a first conductive layer, implanting ions into the first conductive layer, thereby turning at least a surface layer of the first conductive layer amorphous and forming a second conductive layer in connection with the surface layer of the first conductive layer.
According to the present invention, ions are implanted into the first conductive layer, so that at least a surface layer of the first conductive layer may be turned amorphous, and the reactivity at the interface between the first and second conductive layers may be improved. Thus, defects such as a micro void and an interface state may be reduced at the interface between the first and second conductive layers. As a result, the electromigration resistance at the interface improves, and the reliability of the semiconductor device improves. Herein, the conductive layer typically refers to an interconnection or a via in the semiconductor device.
By another method of manufacturing a semiconductor device according to the invention, a multi-layer interconnection structure is formed by a damascene method. According to the manufacturing method, a first interconnection layer including a first interconnection is formed, an interlayer insulating film is formed on the first interconnection layer, and a low dielectric constant film is formed on the interlayer insulating film. Then, a groove for an interconnection is formed in the low dielectric constant film, and a via hole is formed between the first interconnection and the groove in the interlayer insulating film. Ions are implanted into the bottom of the via hole to turn at least a surface layer of the first interconnection amorphous, and the via hole is filled with a conductive material to form a via. The groove is filled with a conductive material to form a second interconnection layer including a second interconnection connected with the via.
According to the present invention, the first interconnection is implanted with ions, so that at least a surface layer of the first interconnection is turned amorphous, and the reactivity between th
Hayes & Soloway P.C.
Meier Stephen D.
NEC Electronics Corporation
Vockrodt Jeff
LandOfFree
Method of manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3146559