Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
2002-04-02
2003-12-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
Reexamination Certificate
active
06670262
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the invention relates to a method of forming a gate electrode of a MOSFET by the use of a photolithographic process and an etching process.
2. Description of the Background Art
FIGS. 27 through 33
show a background art method of manufacturing a semiconductor device in order of process steps. In
FIGS. 27 through 33
, top plan views are labelled (A), and sectional views showing sectional structures taken along a line X
100
—X
100
in the top plan views are labelled (B).
With reference to
FIG. 27
, an impurity is initially introduced into an upper surface of a silicon substrate
101
to form a well
102
. In this step, a p well is formed when a p type impurity such as phosphorus is introduced, and an n well is formed when an n type impurity such as boron is introduced. Next, a trench-type isolating insulation film
103
made of silicon oxide or the like is partially formed in the upper surface of the silicon substrate
101
by a known trench isolation technique. Referring to the top plan view labelled (A) in
FIG. 27
, a portion in which the isolating insulation film
103
is not formed serves as a device formation region for formation of a MOSFET. In other words, the device formation region is defined by the isolating insulation film
103
.
Referring to
FIG. 28
, a silicon oxide film
104
is formed entirely on the well
102
and the isolating insulation film
103
by a CVD process using TEOS (Tetra Ethyl Ortho Silicate) as a source gas. Next, a polysilicon film
105
is formed entirely on the silicon oxide film
104
by a CVD process. Then, a silicon oxide film
106
is formed entirely on the polysilicon film
105
by a thermal oxidation process or a CVD process using TEOS as a source gas. Next, a negative photoresist
107
is applied entirely onto the silicon oxide film
106
.
Referring to
FIG. 29
, the photoresist
107
is exposed to light using a photomask
110
having a pattern in which openings
111
(designated by the reference characters
111
i
to
111
k
in
FIG. 29
) are formed over respective regions wherein gate electrodes are to be formed, that is, using the photomask
110
having an opening pattern similar to a gate electrode layout pattern. The photomask
110
has a structure such that a light shielding film
109
is formed on a glass substrate
108
. With reference to the top plan view labelled (A) in
FIG. 29
, the photomask
110
has a plurality of (in this case, as an example, three) openings
111
i
to
111
k
formed therein. The openings
111
i
and
111
j
are arranged adjacent to each other on the same line extending in a direction of a gate width (in the vertical direction of the figure).
FIG. 30
shows the photoresist
107
after being exposed to light in the step shown in FIG.
29
. With reference to the top plan view labelled (A) in
FIG. 30
, the photoresist
107
has exposed portions
112
(designated by the reference characters
112
i
to
112
k
in
FIG. 30
) formed in corresponding relation to the openings
111
of the photomask
110
.
Referring to
FIG. 31
, a portion (or an unexposed portion) of the photoresist
107
which is not exposed to light in the step shown in
FIG. 29
or a portion of the photoresist
107
other than the exposed portions
112
is removed by development. Thus, only photoresists
113
(designated by the reference characters
113
i
to
113
k
in
FIG. 31
) corresponding to the exposed portions
112
are left on the silicon oxide film
106
.
Referring to
FIG. 32
, the silicon oxide film
106
is patterned using the photoresists
113
. More specifically, using the photoresists
113
as an etch mask, the silicon oxide film
106
is etched by an anisotropic dry etching process which exhibits a higher etch rate in a direction of depth of the silicon substrate
101
. This removes a portion of the silicon oxide film
106
which is not covered with the photoresists
113
, to expose an upper surface of the polysilicon film
105
under the portion. Only silicon oxide films
114
(designated by the reference characters
114
i
to
114
k
in
FIG. 32
) corresponding to the portions of the entirely formed silicon oxide film
106
which are covered with the photoresists
113
are left on the polysilicon film
105
. Thereafter, the photoresists
113
are removed.
Referring to
FIG. 33
, using the silicon oxide films
114
as an etch mask (hard mask), the polysilicon film
105
and the silicon oxide film
104
are etched in the order named by an anisotropic dry etching process which exhibits a higher etch rate in the direction of depth of the silicon substrate
101
. This removes portions of the polysilicon film
105
and the silicon oxide film
104
which are not covered with the silicon oxide films
114
, to expose upper surfaces of the well
102
and the isolating insulation film
103
under the portions. With reference to the sectional view labelled (B) in
FIG. 33
, a gate structure
117
(designated by the reference character
117
k
in
FIG. 33
) having a multi-layer structure such that a silicon oxide film
116
k
, a polysilicon film
115
k
and the silicon oxide film
114
k
are stacked in the order named is formed on the well
102
. The silicon oxide film
116
k
functions as a gate insulation film, and the polysilicon film
115
k
functions as a gate electrode. With reference to the top plan view labelled (A) in
FIG. 33
, gate structures
117
i
and
117
j
each having a multi-layer structure similar to the gate structure
117
k
are formed on the well
102
and the isolating insulation film
103
. The reference numeral
117
is also used hereinafter to generically designate the gate structures
117
i
,
117
j
and
117
k.
Thereafter, a silicon oxide film is formed entirely on the top surface by a CVD process, and is etched back by an anisotropic etching process, thereby forming sidewalls on the side surfaces of each of the gate structures
117
. Next, an impurity is introduced into the upper surface of the well
102
by an ion implantation process to form a pair of source/drain regions on opposite sides of each of the gate structures
117
. MOSFETs are formed by the above-mentioned process steps. Then, an interconnection step is performed, and a semiconductor device is thus completed.
In the background art method of manufacturing the semiconductor device as described above, the photoresist
107
is exposed to light in the step shown in
FIG. 29
, using the photomask
110
having the opening pattern similar to the gate electrode layout pattern. The photoresist
107
is developed to produce the photoresists
113
, and the silicon oxide film
106
is patterned using the photoresists
113
to form the silicon oxide films
114
. Then, etching is performed using the silicon oxide films
114
as a hard mask to form the gate structures
117
.
Unfortunately, when the photoresist
107
is exposed to light in the step shown in
FIG. 29
, corners of the openings
111
are influenced by interference of light, which results in rounded corners of the exposed portions
112
, as shown in FIG.
30
. When a dimension of the openings
111
as measured in a direction of a gate length (in the horizontal direction in the figures) decreases with the decreasing size of the semiconductor device, a dimension of the exposed portions
112
becomes less than a dimension of the openings
111
, as measured in the direction of the gate width. Since the shape of the exposed portions
112
is reflected finally in the shape of the gate structures
117
, a finished dimension of the gate structures
117
is less than the dimension of the openings
111
, as measured in the direction of the gate width. Thus, the background art method of manufacturing the semiconductor device has a problem such that the finished shape of the gate structures
117
recedes from the shape of the openings
111
of the photomask
110
, as seen in the direction of the gate width, which results from the use of the single photom
Nii Koji
Okada Yoshinori
Le Thao P
Nelms David
Renesas Technology Corp.
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