Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

1999-01-05

2003-07-15

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S626000, C438S712000, C438S714000, C438S737000, C438S743000

Reexamination Certificate

active

06593230

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a multi-layer wiring structure, and, in particular, to a method of manufacturing a semiconductor device including a process of forming via holes having different depths by etching an insulating film such as an oxide film.
2. Description of the Related Art
FIG. 1
shows a sectional view of a semiconductor device of the related art in a condition in which via holes have been formed. An interlayer insulating film
8
is formed on a semiconductor substrate
2
including a device-isolating region
4
and a gate electrode
6
. On the interlayer insulating film
8
, wiring layers
16
(
16
a
,
16
b
) are formed, as a result of AlCu films
10
(
10
a
,
10
b
), Ti films
12
(
12
a
,
12
b
) and TiN films
14
(
14
a
,
14
b
) being deposited, at predetermined positions. On the interlayer insulating film
8
including the wiring layers
16
a
,
16
b
, an interlayer insulating film
18
is formed and is planarized through conventional planarization. In the interlayer insulating film
18
, a shallow via hole
20
a
and a deep via hole
20
b
are formed above the wiring layers
16
a
and
16
b
, respectively.
When such via holes having different depths are formed through conventional dry etching, an underlying pattern located below a shallow via hole is damaged seriously in comparison to an underlying pattern located below a deep via hole. As a result of the damage, the contact resistance value of the via hole increases, variation of the contact resistance value of the via hole increases and, thus, reliability of a semiconductor device is degraded.
For example, in a case where inter-wiring-layer via holes are formed, through conventional dry etching, when underlying wiring layers
16
a
,
16
b
include AlCu films
10
a
,
10
b
, Ti films
12
a
,
12
b
and TiN films
14
a
,
14
b
, a via hole
20
a
in which both the TiN film
14
a
and the Ti film
12
a
of the underlying wiring layer
16
a
are etched through to the bottom thereof and a via hole
20
b
in which the TiN film
14
b
and the Ti film
12
b
of the underlying wiring layer
16
b
remain are formed above the same substrate
2
depending on thickness of a planarized interlayer film
18
. In particular, in the via hole
20
a
in which the TiN film
14
a
and the Ti film
12
a
are etched through to the bottom thereof, Al of the AlCu film
10
a
of the underlying wiring layer
16
a
reacts to a gas of a CF family which is an etchant, and a low-volatile fluoride
22
is formed and is deposited on the sidewall of the via hole
20
a
. The fluoride
22
increases the contact resistance of the via hole
20
a
and increases variation of the resistance value. Further, during a degassing process on the order of 500° C. performed before an upper wiring layer is formed, Al of the AlCu film
10
a
, exposed at the bottom of the via hole
20
a
as a result of the TiN film
14
a
and the Ti film
12
a
being etched through to the bottom thereof, may blow out, and, as a result, short-circuiting between wiring patterns may occur.
Thus, when via holes having different depths are formed in a conventional etching method, damage caused to underlying patterns located below the via holes is different depending on the depths of the via holes. In particular, reliability of a shallow via hole is greatly degraded.
In order to solve such a problem, methods which will be described below have been proposed.
In order to eliminate the difference between etching times required for forming respective via holes due to the level difference between respective metallic wiring layers caused by field oxide layers or the like, the following method has been proposed in Japanese Laid-Open Patent Application No. 7-122634: An interlayer insulating film including a film having a low etching rate, a film having a high etching rate and a film having a low etching rate when a predetermined etching gas is used, in the stated order, is formed, wherein each film having the low etching rate has a uniform thickness and the film having the high etching rate has a planer surface. In this method, an organic silicon compound including a CF radical is used as the film having the high etching rate. In the interlayer insulating film formed on the respective metallic wiring layers, although the thickness of each layer having the low etching rate is uniform, the thickness of the layer having the high etching rate varies. However, because the etching time required for forming the via holes in the film having the high etching rate is approximately equal regardless of the depth, it is possible to equalize the etching times required for forming the respective via holes.
Another method has been proposed in Japanese Laid-Open Patent Application No. 9-148270. In this method, for a variation in a film thickness of a film to be etched which variation is caused by an underlying structure (a level variation, etc.), an etching mask is formed such that aspect ratios (depths of via holes/diameters of the via holes) after etching of the via hole formed in a thin-film area and the via hole formed in a thick-film area are approximately equal to each other. As a result of the aspect ratios of the respective via holes being approximately equalized, etching completion times required for forming the via holes are approximately equalized, and, thereby, underlying patterns are prevented from being adversely affected.
Another method has been proposed in Japanese Laid-Open Patent Application No. 8-236619. In this method, an interlayer insulating film is a multi-layer film, and the respective films of the multi-layer film are deposited such that the etching rate increases sequentially starting from the substrate-side film, that is, the film having an etching rate which is extremely low in comparison to the other insulating films is formed nearest to the substrate. By using such an interlayer insulating film, the etching margin is ensured even at a thin part of the interlayer insulating film, and, thus, over-etching at the thin part thereof is prevented.
Another method has been proposed in Japanese Laid-Open Patent Application No. 9-17862. In this method, on a wiring pattern above which a via hole is formed and a planarized interlayer insulating film is thin, a film of a material having a low etching rate is previously formed. As a result of the film of the material having the low etching rate being formed at a specific position, an etching margin is ensured even at a thin part of the interlayer insulating film, and, thus, over-etching at the thin part thereof is prevented.
However, in the method disclosed in Japanese Laid-Open Patent Application No. 7-122634, the organic silicon compound including the CF radical is used as the film having the high etching rate. If this film is exposed on the sidewall of the via hole at a time of photoresist removal using O
2
after etching, a chemical reaction occurs, and, thereby, the via hole may be damaged. In order to prevent this film from being exposed inside the via hole, it is necessary to perform an etch-back process such that the organic silicon compound is prevented from remaining at a position at which the via hole is formed. As a result, a number of processes to be performed increases, and variation in thickness of the interlayer insulating film increases.
In the method disclosed in Japanese Laid-Open Patent Application No. 9-148270, in order to equalize the etching times required for forming the via holes having the different depths, it is necessary to vary the diameters of the via holes depending on the depths thereof. Such a manner is not a practical one.
In the method disclosed in Japanese Laid-Open Patent Application No. 8-236619, etching is performed on the plurality of films having different etching rates at the same time. Therefore, control of the shapes of the via holes is difficult.
In the method disclosed in Japanese Laid-Open Patent Application No. 9-17862, the process of previously forming the film of the material

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