Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Plural fluid growth steps with intervening diverse operation
Reexamination Certificate
2000-08-11
2003-07-15
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Plural fluid growth steps with intervening diverse operation
C438S231000, C438S264000, C438S435000, C438S583000, C438S589000, C438S655000
Reexamination Certificate
active
06593217
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a semiconductor device, such as a logic-type device of the MPU (Micro Processing Unit), as well as to a method of manufacturing the same, where contact resistance between source lines and source regions, on the one hand, and drain lines and drain regions, on the other hand, is reduced.
2. Description of the Background Art
As for contact holes opened for connecting the silicon substrate and metal lines electrically, it is desirable to make the diameters small in order to miniaturize the semiconductor device, while it is desirable to make the diameters large in order to form contacts of low resistance. Therefore, the contact hole forming technology has come to occupy an increasingly important position as the miniaturization of semiconductor devices progresses. In general, on the bottoms of the contact holes, a metal silicide film is formed with the purpose of reducing the contact resistance between the silicon substrate and the metal film.
FIG. 25
is a cross sectional view of a film forming stage of an interlayer insulation film
108
made of a PSG (Phosphate Silicate Glass) film or a BPSG (Boro-Phosphate Silicate Glass) film or the like over the entire surface of the silicon substrate in a manufacturing method according to a prior art. An element isolating insulation film
102
for separating each element forming region, impurity regions
107
which become source and drain regions, a gate insulation film
103
, a gate electrode
105
having side walls
106
, and an interlayer insulation film
108
for covering the gate electrode and the impurity regions (the source and the drain regions)
107
.
A method of manufacturing semiconductor devices up until this stage according to a prior art is as follows. First, the element isolating insulation film
102
is formed on the silicon substrate
101
and each of the element forming regions is separated. Next, a gate insulation film
103
is formed over the entire surface of the silicon substrate, then a polycrystalline silicon film
104
is formed over the entire surface of the silicon substrate, which is patterned to form the gate electrode
105
. Here, though an example where a polycrystalline silicon single layer is used as a gate electrode is shown, a gate electrode of a so-called polycide structure where a metal silicide is layered on the polycrystalline silicon may be used. Next, side walls
106
are formed on the both sides of the gate electrode and the impurity regions
107
which become the source and the drain regions are formed in the silicon substrate
101
on the outside of the side walls
106
. After ion implantation, heat treatment follows in order to activate implanted ion materials in the impurity regions
107
. After this, as shown in
FIG. 25
, an interlayer insulation film
108
is formed.
Next, as shown in
FIG. 26
, contact holes
109
are opened at predetermined positions above the gate electrode
105
and the impurity regions. Next, a metal film
110
which becomes a contact layer and a metal film
111
which becomes a barrier layer are formed in sequence (FIG.
27
). Here, the barrier layer
111
is provided in order to prevent the silicon and the metal line from reacting with each other. Then, by heat treatment, a metal silicide
112
is formed by turning the metal layer
110
of the contact layer formed on the bottom of the contact holes into a silicide through the heat treatment (FIG.
28
). After that, a metal film
113
for lines of a conductive film is formed from tungsten or the like for forming lines ( FIG.
29
), and the metal film for lines is etched to form metal lines
114
(FIG.
30
). In
FIG. 31
, an enlarged view of the part C of
FIG. 30
is shown. On the bottom of the contact holes
109
, the metal silicide layer
112
is formed and between the metal lines
114
and the metal silicide layer
112
, the barrier metal
111
is formed in order to prevent the metal lines and the silicon from reacting with each other.
The contact resistance of those contact parts are determined by the sum of the resistance of the metal lines
114
, an interface resistance between the metal lines
114
and barrier layer
111
, the resistance of barrier layer
111
, an interface resistance between the barrier layer
111
and the metal silicide layer
112
, the resistance of the metal silicide layer
112
and an interface resistance between the metal silicide layer
112
and the source and the drain regions
107
. Among those factors, however, the interface resistance between the metal silicide layer
112
and the source and the drain regions is the largest compared to other resistance, and therefore this interface resistance dominates the contact resistance.
Here, the interface resistance between the metal silicide layer
112
and the source and the drain regions
107
at issue is represented by the following equation.
The interface resistance
R=&rgr;/S
(1)
wherein &rgr; is an interface resistivity of the interface between the metal silicide layer and the silicon substrate and S is a contact area of the interface between the metal silicide layer and the silicon substrate.
Because of the miniaturization and the higher integration of semiconductor devices which are steadily progressing year after year, the contact hole diameter is being reduced with smaller contact area S of the interface between the metal silicide layer and the silicon substrate resulting in a problem of increasing contact resistance. To solve this problem of increasing contact resistance, the following two methods can be considered based on the above described equation (1).
(A) reducing the interface resistivity &rgr; of the interface between the silicon substrate and the metal silicide layer.
(B) expanding the contact area S of the interface between the silicon substrate and the metal silicide layer.
A prior art where the contact resistance is reduced by focusing on the expansion of the contact area of the above (B) is described. The method for expanding the contact area S is largely categorized into (a) a method of expanding the interface between the silicon substrate and the metal silicide in the direction of wafer thickness, (b) a method of expanding the interface in the direction parallel to the wafer surface, and (c) a method of increasing the interface area between the silicon substrate and the metal silicide at the bottom of the contact holes.
(a) The method of expanding the interface in the direction of the wafer thickness is the most effective method with respect to the point that the miniaturization of the semiconductor device is attained while the contact resistance can be reduced even when the hole diameter is scaled down without expanding the area of the plane of the contact portion. As an example using this method, there is a method for forming a trench in the impurity region of the semiconductor substrate followed by filling in the trench with metal or metal silicide over which a contact hole is formed (see Japanese Patent Laying-Open No. 60-187060). This method has a problem that the number of steps of the process increases because a trench forming step in the silicon substrate and a contact hole forming step are carried out separately.
As an example using the method (b) of expanding in the direction parallel to the wafer surface, there is a method of forming a metal silicide layer having broader area than that of the contact hole cross section (see Japanese Patent Laying-Open No. 8-172125). This method, however, has a shortcoming that the step of forming the metal silicide layer with broader area than that of the contact hole cross section becomes complicated, which increases the cost.
As an example using (c) the method (c) of increasing the above interface area on the contact hole bottom, there is a method of forming a micro unevenness on the contact hole bottom (see Japanese Patent Laying-Open No. 3-280532). This method has an advantage that
Anya Igwe U.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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