Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into...
Reexamination Certificate
2001-04-30
2002-10-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
C438S514000, C438S522000, C438S527000
Reexamination Certificate
active
06461946
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device suitable for manufacturing memory devices and information processing units. More particularly, the invention is concerned with improvements in increasing the breakdown voltage of element isolation, irrespective of the direction of a well boundary.
2. Description of the Background Art
FIG. 39
is a plan view schematically illustrating a main surface of a semiconductor substrate of a semiconductor device before semiconductor elements are formed thereon, the substrate having on its surface wells for element isolation. In the main surface of the semiconductor substrate
100
, a STI (Shallow Trench Isolation)
2
as an element isolation structure is selectively formed, and a plurality of element regions
1
are separated from one another, by the STI
2
. The pattern shape of the STI
2
is variously set depending on the application of the semiconductor device. The pattern shape shown in
FIG. 39
is a simple model that is supposed for convenience of explanation.
FIG. 40
is a sectional view taken along the line A—A of
FIG. 39. A
P well
4
or an N well
5
is disposed in each element region
1
, and a boundary (called “well boundary”)
6
between the wells
4
and
5
having different conductivity types is disposed directly below the STI
2
. The main surface of the semiconductor substrate
100
is covered with an insulating film
3
, together with the STI
2
. After forming the P well
4
and N well
5
, semiconductor devices, e.g., MOSFETs, are formed thereon, which are not shown in FIG.
40
. Thereby, the semiconductor elements are isolated from each other, by the STI
2
and the well boundary
6
directly therebelow. That is, the P well
4
and N well
5
are aimed at element isolation.
FIGS. 41 and 42
are diagrams of the steps of forming a P well
4
and an N well
5
. Referring to
FIG. 41
, a resist
8
, which is patterned such that an opening is selectively provided in a region where a P well
4
should be formed, is disposed on a main surface of a semiconductor substrate
100
. By using the resist
8
as a shield, a P type impurity ion
14
is implanted to selectively form the P well
4
. In order to avoid channeling derived from the crystal structure of the semiconductor substrate
100
, the impurity implantation is performed with the implantation direction tilted from about 3 to about 15° from the normal of the main surface. Implantation energy is set to a range from 100 to 500 keV, for example. The resist
8
is then removed when the implantation is completed.
Referring to
FIG. 42
, a resist
9
, which is patterned such that an opening is selectively provided in a region where an N well
5
should be formed, is disposed on the main surface of the semiconductor substrate
100
. By using the resist
9
as a shield, an N type impurity ion
15
is implanted to selectively form the N well
5
. Implantation direction and energy is the same as in the step of FIG.
41
. The resist
9
is then removed when the implantation is completed.
Through the foregoing steps, there is obtained the structure of
FIG. 40
before semiconductor elements are disposed thereon. The same structure can be obtained even if the order of the steps of
FIGS. 41 and 42
is reversed.
However, since the impurity ion is implanted in a direction tilted with respect to the normal of a wafer, the following problem will arise depending on the relationship between the implantation direction and the direction of well boundary
6
. Specifically, the structure of
FIG. 43
that departs from the ideal form of
FIG. 40
, might be made due to the shadowing effect of preventing implantation toward the shadow portion of the resist
8
, as shown in
FIG. 41
, or the effect of unnecessary implantation up to the direct underside of the resist
9
, as shown in FIG.
42
. In the structure of
FIG. 43
, the well boundary
6
is deviated distance D from the desired position.
It is known that the deviation of the well boundary
6
degrades the element isolation capability of wells, namely, the breakdown voltage of element isolation. It is also known that this degradation is more remarkable with decreasing widths W
1
and W
2
of the STI
2
(called “isolation width”) shown in FIG.
39
. It is however the modem trend that the isolation width is being made narrower as the high integration of semiconductor devices is advanced.
Referring again to
FIG. 39
, it is possible to select the ion implantation direction so as not to cause any deviation of the well boundary
6
. along the STI
2
extending in a single direction (e.g., side to side on FIG.
25
). In this case, however, the well boundary
6
along the STI
2
extending in another direction (e.g., up and down on
FIG. 25
) suffers from a noticeable deviation. For preventing this, if the isolation width W
2
is made wider than the isolation width W
1
, the high integration of semiconductor devices is hindered. This can also be one factor in hindering the degree of freedom of layout.
Thus, it has conventionally been impossible to increase the breakdown voltage of element isolation by eliminating the deviations of all the well boundaries
6
, without depending on their directions, at the same time that the isolation width is uniformly set to a small value, in order to ensure both the high integration of a semiconductor device and the degree of freedom of layout design.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method of manufacturing a semiconductor device comprises the steps of: (a) preparing a semiconductor substrate having a main surface; (b) with M (M≧2) implantation types defined by combination of an impurity element and its implantation energy, performing an impurity implantation to the main surface through a plurality of shields disposed on the main surface, thereby to selectively form a P well and an N well adjacent each other in the main surface, and, for N (1≦N≦M) types of the M implantation types, performing the implantation from a plurality of directions such that projecting components of a vector indicating an implantation direction toward the main surface are cancelled with each other; and (c) forming a semiconductor element in each of the P well and the N well.
According to a second aspect, the method of the first aspect is characterized in that in the step (b), for each of the N implantation types, the implantation is performed from the plurality of directions such that the projecting components are cancelled with each other.
According to a third aspect, the method of the second aspect is characterized in that in the step (b), the N equals the M.
According to a fourth aspect, the method of the first aspect is characterized in that in the step (b), the N is 2 or more, and the implantation is performed from the plurality of directions such that the projecting components are cancelled with each other, between different implantation types.
According to a fifth aspect, the method of the fourth aspect is characterized in that in the step (b), the N equals the M, the conductivity type of the impurity element differs between the different implantation types, and the implantation is performed from the plurality of directions such that the projecting components are cancelled with each other, between all implantation types of N type impurity and all implantation types of P type impurity.
According to a sixth aspect, the method according to any of the first to fifth aspects is characterized in that in the step (b), the plurality of directions are two directions selected such that the projecting components are opposed to each other on a line along the main surface.
According to a seventh aspect, the method according to any of the first to fifth aspects is characterized in that in the step (b), the plurality of directions are four directions selected such that the projecting components are opposed to each other on two lines that cross each other at right angles along the main surface.
According to a
Eikyu Katsumi
Kitani Takeshi
Sugiyama Masao
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