Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-12-27
2002-10-08
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S630000, C438S648000, C438S675000, C438S680000
Reexamination Certificate
active
06461957
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention concerns a semiconductor device and a method of manufacturing the same. In particular, it relates to a method of manufacturing a memory semiconductor device having a fine connection plug, a high performance logic semiconductor device having a fine connection plug or a local wiring. It also relates to a memory/logic embedded LSI having a memory circuit and a logic circuit together.
2. Description of Related Art
In semiconductor devices now under development for higher integration density, application of a conductive layer formed by stacking a low resistance material layer and a silicon layer such as a metal silicide layer/silicon layer or a metal layer/metal nitride layer/silicon layer instead of an existent single silicon layer has been started (layer constitution expressed by A/B means that A is an upper layer and B is a lower layer). This is because the stacked conductive layer is effective for the lowering of the sheet resistance of the conductive layer itself or reduction of contact resistance between the conductive layer and the interconnection layer disposed above it.
A first application example of the stacked conductive layer is source and drain areas of MOS (Metal Oxide Semiconductor) transistors. A structure of stacking to form a silicide layer of a metal such as titanium or cobalt on the entire surface of an impurity-doped diffusion layer comprising silicon instead of a diffusion layer of a silicon mono-layer has been used for a logic semiconductor device such as in a high speed processor. Further, study has also been made on a nickel silicide layer. When the metal silicide layer is formed over the entire surface of the diffusion layer such that both the diffusion layer resistance and the contact resistance between the diffusion layer and the upper interconnection layer are reduced. There is another technique for forming a silicide layer of metal such as titanium, cobalt or nickel on polysilicon of a gate layer simultaneously with source and drain areas so as to obtain a gate layer as a stack of metal silicide layer/polysilicon layer, which also reduces the layer resistance of the gate layer.
The method for forming the metal silicide layer on the diffusion layer also includes a method for forming a suicide layer of a metal, such as titanium, only at the bottom of a through hole on the diffusion layer after etching the through hole to the diffusion layer rather than forming the metal silicide layer over the entire surface of the diffusion layer area. This intends to reduce the contact resistance between the metal interconnection layer and the metal silicide layer is formed only at the bottom of the through hole between the metal interconnection layer and the diffusion layer. Subsequently, a contact plug for burying the through hole (hereinafter simply referred to as “plug”) is formed. This method is generally used for various semiconductor devices besides memory semiconductor devices.
A second application example of the stacked conductive layer is a gate layer of an MOS transistor. Layers of lower resistance have been used for a polysilicon mono-layer for the gate layer, a stacked gate layer of metal silicide layer/polysilicon layer, and a stacked gate layer of metal layer/metal nitride layer/polysilicon layer. Furthermore, a study on a laminate gate comprising a metal layer/metal nitride layer excluding the polysilicon layer has also been started.
In view of the application of the stacked conductive layer as described above, there is a demand for forming a conductive layer providing satisfactory electric contact to the surface of a lower layer comprising different materials at the bottom of the through holes after etching the through holes for connecting a diffusion layer and an interconnection layer or for connecting a gate layer and an interconnection layer, or after etching the through holes further for connecting plugs to each other.
For example, it has now been required to form a conductive layer providing satisfactory electric contact both for a metal silicide layer and a metal layer at the bottom of the through holes etched on the gate layer comprising a metal silicide layer/polysilicon layer, a metal layer/metal nitride layer/polysilicon layer, and a silicon layer at the bottom of the through holes etched on the silicon layer. Further, if a metal silicide is formed over the entire surface of the diffusion layer, it is necessary to form a conductive layer providing satisfactory electrical contact both for a metal silicide layer at the bottom of the through holes etched on a metal silicide layer/silicon layer of a diffusion layer and for a metal layer at the bottom of the through holes etched on a gate layer comprising a metal layer/metal nitride layer/polysilicon layer.
For example, in an embedded LSI where a logic circuit and a DRAM (Dynamic Random Access Memory) circuit are integrated on a single semiconductor device, or in a DRAM in which a metal silicide film identical with that in a logic semiconductor device formed to a diffusion layer of a peripheral circuit area of a high speed memory, it is necessary to form a conductive layer providing satisfactory electric contact both for the diffusion layer in which a metal silicide layer is formed on the surface of a peripheral circuit areas of a logic circuit and for a plug layer at the bottom of the through holes etched to a plug layer comprising impurity-doped polysilicon in the memory array area.
To avoid hindering the miniaturization of the semiconductor device or complicating manufacturing steps, it is necessary to form a conductive layer in one single step at the bottom of each of the through holes having a lower layer surface comprising different materials as described above.
Further, it has become necessary to form a conductive layer film in one single step at the bottom of a group of through holes of different depth, through holes or openings for local interconnections of different shape and size for the etched area so as to produce smaller and more complicated high performance semiconductor devices. Particularly, the local interconnection technique is indispensable for miniaturization and higher performance of the logic semiconductor device, and the shape of the etched area of openings for local interconnection (hereinafter simply referred to as “local interconnection hole”) is generally formed in a rectangular shape with a long side to short side ratio of 2 or more, in a rectangular shape or in an L-shape in which a longitudinal portion has a rectangular shape. The local interconnection is formed by burying the local interconnection hole with a metal layer.
For forming a conductive layer at each of the bottoms for the group of through holes or local interconnection holes having a lower layer surface comprising different materials as described above, or for forming a conductive layer film in one single step to each bottom of the through holes of different depths and to each bottom of the through holes or local interconnection holes having different shapes and sizes of etched area, a manufacturing method of forming a metal film is used. The method includes sputtering, such as titanium, reacting at least a portion of a metal layer in contact with a silicon layer or a metal silicide layer at the bottom of the through holes or local interconnection holes by heat treatment at about 700° C. thereby additionally forming a metal silicide layer so as to reduce the contact resistance to silicon. The heat treatment is conducted just after the sputtering step or the reacting step.
The method is mainly used to provide a titanium silicide layer. The metal silicide layer is necessary for reducing the contact resistance between the silicon layer or silicon-containing metal silicide layer and an upper metal interconnection layer. Particularly, in the plug or local interconnection to silicon, when the plug or interconnection is formed, such as of titanium nitride, since the contact resistance increases if a reaction barrier layer comprising titanium n
Kawano Masakazu
Yokoyama Natsuki
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