Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-07-10
2002-08-06
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S783000, C438S633000, C438S723000
Reexamination Certificate
active
06429105
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of forming a metal interconnect line using a CMP (Chemical Mechanical Polishing) process. The invention relates also to a semiconductor device manufactured by the above-mentioned method.
2. Description of the Background Art
A semiconductor integrated circuit comprises a multiplicity of semiconductor devices formed on a main surface of a semiconductor substrate in a device formation region. The semiconductor devices are electrically isolated from each other by an isolating insulation film such as STI (Shallow Trench Isolation) formed in the main surface of the semiconductor substrate in an isolation region. To accomplish the function of the semiconductor integrated circuit, the semiconductor devices are electrically connected to each other by an electrical conductor such as an interconnect line.
The electrical conductor commonly used includes metal or heavily doped polysilicon. The material of the metal interconnect line is aluminum, copper, tungsten, molybdenum, or the like. The material of a gate electrode which is an interconnect line formed on the main surface of the semiconductor substrate is aluminum, polysilicon, a two-layer structure comprised of polysilicon and metal silicide, tungsten, molybdenum, or the like. Metal used for the metal silicide is tungsten, cobalt, nickel, titanium, zirconium, platinum, or the like.
With recently decreasing size of semiconductor integrated circuits, the operating speed of semiconductor devices has been dominated by the performance of multi-level interconnect lines, rather than the performance of MOS transistors themselves, since a 0.18-&mgr;m line width generation. In recent years, attention has accordingly been focused on a copper interconnect line having a resistivity lower than that of an aluminum interconnect line which has been a conventionally dominant metal interconnect line. At 20° C., copper has a resistivity of 1.70 &mgr;&OHgr;·cm, whereas aluminum has a resistivity of 2.74 &mgr;&OHgr;·cm.
Since aluminum is anisotropically etchable, a conventional process for forming an aluminum interconnect line comprises depositing an aluminum film on an entire wafer surface, forming a photoresist on the aluminum film by a photolithographic process, and anisotropically etching the aluminum film by using the photoresist as a mask. On the other hand, a technique for anisotropically etching copper has not yet been currently established. To form a copper interconnect line, a process known as a damascene process is employed which comprises anisotropically etching an interlayer insulation film to form a trench, forming a copper film on an entire surface of the interlayer insulation film so as to fill the trench by an electroplating or CVD process, and polishing away an excess part of the copper film which is formed on the interlayer insulation film by a CMP process to form a copper interconnect line in the trench.
FIG. 15
is a cross-sectional view of a background art semiconductor device comprising copper interconnect lines formed using the damascene process. A channel stopper
102
in the form of a layer is formed in a p-type semiconductor substrate
101
. An STI
103
is formed in a main surface of the semiconductor substrate
1
in an isolation region. An nMOS transistor is manufactured in the semiconductor substrate
101
in a device formation region. The nMOS transistor comprises: a gate structure
106
selectively formed on the main surface of the semiconductor substrate
101
and having a multi-layer structure including a gate insulation film
104
and a gate electrode
105
formed on the gate insulation film
104
; an insulation film
107
and a sidewall
108
which cover upper and side surfaces of the gate structure
106
; and source/drain regions selectively formed in the main surface of the semiconductor substrate
101
and including n
−
type doped regions
109
of a relatively low concentration and n
+
type doped regions
110
of a relatively high concentration. A metal silicide
111
is formed on and in an upper surface of the doped regions
110
.
An FSG (fluorosilicate glass) film
112
is formed on entire surfaces of the STI
103
and nMOS transistor, and a silicon nitride (Si
3
N
4
) film
113
is formed on an entire surface of the FSG film
112
. Contact holes
114
extending from an upper surface of the silicon nitride film
113
to an upper surface of the metal silicide
111
are selectively formed in the FSG film
112
and the silicon nitride film
113
. A barrier metal
115
is formed on a side surface of each of the contact holes
114
, and a tungsten plug
116
is formed to fill each of the contact holes
114
with the barrier metal
115
formed on the side surface thereof.
An FSG film
117
is formed on an entire surface of the silicon nitride film
113
, and a silicon oxynitride (SiON) film
118
is formed on an entire surface of the FSG film
117
. Contact holes
119
extending from an upper surface of the silicon oxynitride film
118
to an upper surface of the tungsten plugs
116
are selectively formed in the FSG film
117
and the silicon oxynitride film
118
. A barrier metal
120
is formed on side and bottom surfaces of each of the contact holes
119
, and a copper interconnect line
121
is formed to fill each of the contact holes
119
with the barrier metal
120
formed on the side and bottom surfaces thereof. A silicon nitride film
122
is formed on an entire surface of the silicon oxynitride film
118
.
A TEOS (tetraethylorthosilicate) film
123
is formed on an entire surface of the silicon nitride film
122
, and an FSG film
124
is formed on an entire surface of the TEOS film
123
. A silicon oxynitride film
125
is formed on an entire surface of the FSG film
124
. A contact hole
126
extending from an upper surface of the silicon oxynitride film
125
to an upper surface of one of the copper interconnect lines
121
is selectively formed in the TEOS film
123
, the FSG film
124
and the silicon oxynitride film
125
. A barrier metal
127
is formed on side and bottom surfaces of the contact hole
126
, and a copper interconnect line
128
is formed to fill the contact hole
126
with the barrier metal
127
formed on the side and bottom surfaces thereof. More specifically, part of the copper interconnect line
128
which lies below an upper surface of the TEOS film
123
functions as a copper plug for establishing an electric connection between the lower-level copper interconnect line
121
and part of the upper-level copper interconnect line
128
which lies above the upper surface of the TEOS film
123
.
A trench
129
extending from the upper surface of the silicon oxynitride film
125
to a bottom surface of the FSG film
124
is selectively formed in the FSG film
124
and the silicon oxynitride film
125
. A barrier metal
130
is formed on side and bottom surfaces of the trench
129
, and a copper interconnect line
131
is formed to fill the trench
129
with the barrier metal
130
formed on the side and bottom surfaces thereof. A silicon nitride film
132
is formed on an entire surface of the silicon oxynitride film
125
. The components ranging from a bottom surface of the TEOS film
123
to an upper surface of the silicon nitride film
132
serve as a single unit
133
of an interconnect layer. A protective film
134
is formed on an entire surface of the silicon nitride film
132
.
The barrier metals
120
,
127
,
130
have the function of preventing copper atoms constituting the copper interconnect lines
121
,
128
,
131
from diffusing or drifting into the FSG films
117
,
124
to degrade an insulating property.
A process for forming only the copper interconnect line
131
and the part of the copper interconnect line
128
which lies above the upper surface of the TEOS film
123
in the single interconnect layer unit
133
is known as a single damascene process. On the other hand, a process for f
Everhart Caridad
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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