Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-10-18
2002-10-15
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S653000, C438S659000, C438S532000
Reexamination Certificate
active
06465335
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a structure of a semiconductor device, and more particularly, it relates to a method of forming a gate electrode of a MISFET (metal insulator semiconductor field-effect transistor) and a structure thereof.
2. Description of the Background Art
The gate length of a MISFET is reduced following refinement of a semiconductor device, while sheet resistance as well as contact resistance of a gate electrode are increased. When such resistance is increased, the operating speed of a circuit is slowed down and the following problem is caused: In a DRAM (dynamic random access memory), for example, the length of word lines must be reduced in order to compensate for increase of wiring resistance resulting from reduction of a wiring sectional area, and hence the number of memory cells connectable to each word line is reduced. Therefore, the number of necessary sectional word lines as well as the number of peripheral circuits such as sense amplifiers are increased, leading to the increase of the chip area. Consequently, the number of chips per wafer is reduced, resulting in increase of the manufacturing cost.
Therefore, a conventional MISFET uses a gate electrode (the so-called polycide gate) having a two-layer structure of a doped polysilicon layer and a metal silicide layer exhibiting smaller gate resistance than a gate electrode (the so-called polysilicon gate) consisting of only doped polysilicon. For example, a gate electrode having a two-layer structure of a doped polysilicon layer and a cobalt silicide (CoSi
2
) layer or a two-layer structure of a doped polysilicon layer and a tungsten silicide (WSi
x
(2.2≦x≦2.7)) layer is used.
In a refined MISFET having a gate length of not more than 0.12 &mgr;m, however, it is impossible to sufficiently speed up circuit operations by refining the semiconductor device due to large gate resistance also when its gate electrode is formed by a polycide gate. To this end, a gate electrode (the so-called polymetal gate) having a three-layer structure of a polysilicon layer, a barrier layer and a metal layer having smaller gate resistance than the polycide gate has been proposed.
FIG. 29
is a sectional view showing the structure of a conventional semiconductor device comprising a polymetal gate. A multilayer structure obtained by stacking a doped polysilicon layer
102
, a barrier layer
103
, a metal layer
104
, another barrier layer
105
and an insulating layer
106
in this order is formed on the upper surface of a silicon substrate
100
through a gate insulator film
101
.
FIG. 29
omits illustration of element isolation films and source/drain regions.
An impurity is introduced into the doped polysilicon layer
102
in a high concentration (about 1×10
20
to 8×10
20
/cm
3
). More specifically, an n-type impurity such as phosphorus or arsenic is introduced in a surface channel N-type MOSFET or a buried channel P-type MOSFET, while a p-type impurity such as boron is introduced in a surface channel P-type MOSFET or a buried channel N-type MOSFET.
The metal layer
104
is prepared from tungsten or the like, and the barrier layer
103
is prepared from a barrier metal consisting of a metal nitride such as tungsten nitride (WN) or titanium nitride (TiN). When silicon atoms contained in the doped polysilicon layer
102
and metal atoms contained in the metal layer
104
mutually diffuse/react due to heat treatment to form metal silicide in the vicinity of the interface between these layers
102
and
104
, the metal silicide is formed in part of the metal layer
104
since the metal silicide has higher resistance than the metal to increase the resistance of the polymetal gate as a whole. The barrier layer
103
is provided in order to suppress occurrence of such a phenomenon.
However, the conventional semiconductor device comprising the polymetal gate shown in
FIG. 29
has the following problems: As hereinabove described, the doped polysilicon layer
102
is doped with the impurity in a high concentration. When heat treatment is performed during steps of manufacturing the semiconductor device, however, the impurity introduced into the doped polysilicon layer
102
in the vicinity of the interface between the same and the barrier layer
103
thermally diffuses into the barrier layer
103
. Further, the impurity introduced into the doped polysilicon layer
102
in the vicinity of the interface between the same and the gate insulator film
101
thermally diffuses into the gate insulator film
101
. Consequently, the impurity concentration of the doped polysilicon layer
102
is reduced in the vicinity of each of the aforementioned interfaces to cause partial depletion of the layer doped with the impurity, and hence resistance is increased in this portion. Consequently, the resistance of the polymetal gate is also increased as a whole.
When the metal atoms contained in the barrier layer
103
diffuse into the doped polysilicon layer
102
due to heat treatment or the silicon atoms contained in the doped polysilicon layer
102
diffuse into the barrier layer
103
due to heat treatment, the silicon atoms and the metal atoms react with each other to form metal silicide. While there is no problem if the metal silicide is homogeneously formed around the interface between the doped polysilicon layer
102
and the barrier layer
103
, such metal silicide is partially formed in practice. Therefore, the contact resistance on the aforementioned interface is locally increased to disadvantageously increase the resistance of the overall polymetal gate. This problem can also be caused when the metal atoms contained in the metal layer
104
and the silicon atoms contained in the doped polysilicon layer
102
pass through the barrier layer
103
to diffuse to each other.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a method of manufacturing a semiconductor device comprises steps of (a) forming a gate insulator film on a main surface of a semiconductor substrate, (b) forming a first semiconductor film on the gate insulator film which is doped with a prescribed impurity and having at least partially a layer consisting of a material having a higher impurity activation rate than polysilicon, (c) forming a barrier film on the first semiconductor film, (d) forming a metal film on the barrier film and (e) selectively removing the metal film, the barrier film and the first semiconductor film in this order thereby forming a gate electrode.
According to the first aspect, resistance of the gate electrode can be reduced as compared with the case of forming the gate electrode by a first semiconductor film consisting of only polysilicon.
According to a second aspect of the present invention, the first semiconductor film entirely consisting of the layer is formed in the step (b).
According to the second aspect, resistance of the gate electrode can be reduced as compared with the case of forming the gate electrode by a first semiconductor film partially having a layer consisting of a material having a higher impurity activation rate than polysilicon.
According to a third aspect of the present invention, the step (b) includes steps of (b-1) forming a second semiconductor film consisting of the material as the layer and (b-2) forming a third semiconductor film different in impurity activation rate from the second semiconductor film.
According to the third aspect, the threshold voltage of a transistor can be adjusted by adjusting the ratio of the thickness of the second semiconductor film to that of the third semiconductor film.
According to a fourth aspect of the present invention, the second semiconductor film is formed in at least either a part including the interface between the same and the barrier film or a part including the interface between the same and the gate insulator film.
According to the fourth aspect, partial depletion of the layer doped with the impurity can be avoided in the second s
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Thanh
Nguyen Tuan H.
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